Lines Matching +full:0 +full:x00400000

14 #define PA_ROM		0x00000000	/* EPROM */
15 #define PA_ROM_SIZE	0x00400000	/* EPROM size 4M byte */
16 #define PA_FROM		0x01000000	/* EPROM */
17 #define PA_FROM_SIZE	0x00400000	/* EPROM size 4M byte */
18 #define PA_EXT1		0x04000000
19 #define PA_EXT1_SIZE	0x04000000
20 #define PA_EXT2		0x08000000
21 #define PA_EXT2_SIZE	0x04000000
22 #define PA_SDRAM	0x0c000000
23 #define PA_SDRAM_SIZE	0x04000000
25 #define PA_EXT4		0x12000000
26 #define PA_EXT4_SIZE	0x02000000
27 #define PA_EXT5		0x14000000
28 #define PA_EXT5_SIZE	0x04000000
29 #define PA_PCIC		0x18000000	/* MR-SHPC-01 PCMCIA */
31 #define PA_83902	0xb0000000	/* DP83902A */
32 #define PA_83902_IF	0xb0040000	/* DP83902A remote io port */
33 #define PA_83902_RST	0xb0080000	/* DP83902A reset port */
35 #define PA_SUPERIO	0xb0400000	/* SMC37C935A super io chip */
36 #define PA_DIPSW0	0xb0800000	/* Dip switch 5,6 */
37 #define PA_DIPSW1	0xb0800002	/* Dip switch 7,8 */
38 #define PA_LED		0xb0c00000	/* LED */
40 #define PA_BCR		0xb0e00000
42 #define PA_BCR		0xb1400000	/* FPGA */
45 #define PA_MRSHPC	0xb83fffe0	/* MR-SHPC-01 PCMCIA controller */
46 #define PA_MRSHPC_MW1	0xb8400000	/* MR-SHPC-01 memory window base */
47 #define PA_MRSHPC_MW2	0xb8500000	/* MR-SHPC-01 attribute window base */
48 #define PA_MRSHPC_IO	0xb8600000	/* MR-SHPC-01 I/O window base */
63 #define BCR_ILCRA	(PA_BCR + 0)
72 #define INTC_IRR0       0xa4000004UL
73 #define INTC_IRR1       0xa4000006UL
74 #define INTC_IRR2       0xa4000008UL
76 #define INTC_ICR0       0xfffffee0UL
77 #define INTC_ICR1       0xa4000010UL
78 #define INTC_ICR2       0xa4000012UL
79 #define INTC_INTER      0xa4000014UL
81 #define INTC_IPRC       0xa4000016UL
82 #define INTC_IPRD       0xa4000018UL
83 #define INTC_IPRE       0xa400001aUL
99 #define SH_ETH0_BASE 0xA7000000
100 #define SH_ETH1_BASE 0xA7000400
103 # define PHY_ID 0x00
105 # define PHY_ID 0x01