Lines Matching full:7
19 #define PCMCIA_ATTR16 7
24 /* write-read/write-write delay (0-7:0,1,2,3,4,5,6,7) */
27 /* different area, read-write delay (0-7:0,1,2,3,4,5,6,7) */
30 /* same area, read-write delay (0-7:0,1,2,3,4,5,6,7) */
33 /* different area, read-read delay (0-7:0,1,2,3,4,5,6,7) */
36 /* same area, read-read delay (0-7:0,1,2,3,4,5,6,7) */
48 /* Burst pitch (0-7:0,1,2,3,4,5,6,7) */
57 /* address setup before assert CSn for SRAM (0-7:0,1,2,3,4,5,6,7) */
60 /* address hold after negate CSn for SRAM (0-7:0,1,2,3,4,5,6,7) */
63 /* CSn assert to RD assert delay for SRAM (0-7:0,1,2,3,4,5,6,7) */
66 /* RD negate to CSn negate delay for SRAM (0-7:0,1,2,3,4,5,6,7) */
69 /* CSn assert to WE assert delay for SRAM (0-7:0,1,2,3,4,5,6,7) */
72 /* WE negate to CSn negate delay for SRAM (0-7:0,1,2,3,4,5,6,7) */
78 /* wait cycle (0-15:0,1,2,3,4,5,6,7,8,9,11,13,15,17,21,25) */
86 /* wait B (0-15:0,1,2,3,4,5,6,7,8,9,11,13,15,17,21,25) */
88 /* Address->OE/WE assert delay A (0-7:0,1,2,3,6,9,12,15) */
90 /* Address->OE/WE assert delay B (0-7:0,1,2,3,6,9,12,15) */
92 /* OE/WE negate->Address delay A (0-7:0,1,2,3,6,9,12,15) */
94 /* OE/WE negate->Address delay B (0-7:0,1,2,3,6,9,12,15) */
99 (SZ5<<8)|(RDSPL5<<7)|(BW5<<4)|(MPX5<<3)|TYPE5)