powerpc/sysdev/xilinx_intc.c

2  * Interrupt controller driver for Xilinx Virtex FPGAs
13  * This is a driver for the interrupt controller typically found in
16  * The interrupt sense levels are hard coded into the FPGA design with
34 #define XINTC_ISR	0	/* Interrupt Status */
35 #define XINTC_IPR	4	/* Interrupt Pending */
36 #define XINTC_IER	8	/* Interrupt Enable */
37 #define XINTC_IAR	12	/* Interrupt Acknowledge */
38 #define XINTC_SIE	16	/* Set Interrupt Enable bits */
39 #define XINTC_CIE	20	/* Clear Interrupt Enable bits */
40 #define XINTC_IVR	24	/* Interrupt Vector */
47 /* The following table allows the interrupt type, edge or level,
48  * to be cached after being read from the device tree until the interrupt
53 /* Map the interrupt type from the device tree to the interrupt types
54  * used by the interrupt subsystem
64  * The interrupt controller is setup such that it doesn't work well with
65  * the level interrupt handler in the kernel because the handler acks the
66  * interrupt before calling the application interrupt handler. To deal with
142  * xilinx_intc_xlate - translate virq# from device tree interrupts property
150 		return -EINVAL;  in xilinx_intc_xlate()
152 	/* keep a copy of the interrupt type til the interrupt is mapped  in xilinx_intc_xlate()
156 	/* Xilinx uses 2 interrupt entries, the 1st being the h/w  in xilinx_intc_xlate()
157 	 * interrupt number, the 2nd being the interrupt type, edge or level  in xilinx_intc_xlate()
167 	irq_set_chip_data(virq, h->host_data);  in xilinx_intc_map()
181 	.map = xilinx_intc_map,
191 	/* Find and map the intc registers */  in xilinx_intc_init()
194 		pr_err("xilinx_intc: could not map registers\n");  in xilinx_intc_init()
198 	/* Setup interrupt controller */  in xilinx_intc_init()
205 			     &xilinx_intc_ops, -1);  in xilinx_intc_init()
208 	irq->host_data = regs;  in xilinx_intc_init()
215 	void * regs = master_irqhost->host_data;  in xilinx_intc_get_irq()
222  * Support code for cascading to 8259 interrupt controllers
232 	/* Let xilinx_intc end the interrupt */  in xilinx_i8259_cascade()
233 	chip->irq_unmask(&desc->irq_data);  in xilinx_i8259_cascade()
248 		pr_err("virtex_ml510: Failed to map cascade interrupt\n");  in xilinx_i8259_setup_cascade()
256 	/* This looks like a dirty hack to me --gcl */  in xilinx_i8259_setup_cascade()
268 	{ .compatible = "xlnx,opb-intc-1.00.c", },
269 	{ .compatible = "xlnx,xps-intc-1.00.a", },
274  * Initialize master Xilinx interrupt controller
280 	/* find top level interrupt controller */  in xilinx_intc_init_tree()