Lines Matching defs:ccsr_pci

47 struct ccsr_pci {  struct
48 	__be32	config_addr;		/* 0x.000 - PCI/PCIE Configuration Address Register */
49 	__be32	config_data;		/* 0x.004 - PCI/PCIE Configuration Data Register */
50 	__be32	int_ack;		/* 0x.008 - PCI Interrupt Acknowledge Register */
51 	__be32	pex_otb_cpl_tor;	/* 0x.00c - PCIE Outbound completion timeout register */
52 	__be32	pex_conf_tor;		/* 0x.010 - PCIE configuration timeout register */
53 	__be32	pex_config;		/* 0x.014 - PCIE CONFIG Register */
54 	__be32	pex_int_status;		/* 0x.018 - PCIE interrupt status */
55 	u8	res2[4];
56 	__be32	pex_pme_mes_dr;		/* 0x.020 - PCIE PME and message detect register */
57 	__be32	pex_pme_mes_disr;	/* 0x.024 - PCIE PME and message disable register */
58 	__be32	pex_pme_mes_ier;	/* 0x.028 - PCIE PME and message interrupt enable register */
59 	__be32	pex_pmcr;		/* 0x.02c - PCIE power management command register */
60 	u8	res3[3024];
67 	struct pci_outbound_window_regs pow[5];
68 	u8	res14[96];
69 	struct pci_inbound_window_regs	pmit;	/* 0xd00 - 0xd9c Inbound MSI */
70 	u8	res6[96];
75 	struct pci_inbound_window_regs piw[4];
77 	__be32	pex_err_dr;		/* 0x.e00 - PCI/PCIE error detect register */
78 	u8	res21[4];
79 	__be32	pex_err_en;		/* 0x.e08 - PCI/PCIE error interrupt enable register */
80 	u8	res22[4];
81 	__be32	pex_err_disr;		/* 0x.e10 - PCI/PCIE error disable register */
82 	u8	res23[12];
83 	__be32	pex_err_cap_stat;	/* 0x.e20 - PCI/PCIE error capture status register */
84 	u8	res24[4];
85 	__be32	pex_err_cap_r0;		/* 0x.e28 - PCIE error capture register 0 */
86 	__be32	pex_err_cap_r1;		/* 0x.e2c - PCIE error capture register 0 */
87 	__be32	pex_err_cap_r2;		/* 0x.e30 - PCIE error capture register 0 */
88 	__be32	pex_err_cap_r3;		/* 0x.e34 - PCIE error capture register 0 */