include/asm/immap_cpm2.h

569 typedef struct immap {  struct
574 	u8		im_dpram1[16*1024];
575 	u8		res1[16*1024];
576 	u8		im_dpram2[4*1024];
577 	u8		res2[8*1024];
578 	u8		im_dpram3[4*1024];
579 	u8		res3[16*1024];
581 	sysconf_cpm2_t	im_siu_conf;	/* SIU Configuration */
582 	memctl_cpm2_t	im_memctl;	/* Memory Controller */
583 	sit_cpm2_t	im_sit;		/* System Integration Timers */
584 	pci_cpm2_t	im_pci;		/* PCI Controller */
585 	intctl_cpm2_t	im_intctl;	/* Interrupt Controller */
586 	car_cpm2_t	im_clkrst;	/* Clocks and reset */
587 	iop_cpm2_t	im_ioport;	/* IO Port control/status */
588 	cpmtimer_cpm2_t	im_cpmtimer;	/* CPM timers */
589 	sdma_cpm2_t	im_sdma;	/* SDMA control/status */
591 	fcc_t		im_fcc[3];	/* Three FCCs */
592 	u8		res4z[32];
593 	fcc_c_t		im_fcc_c[3];	/* Continued FCCs */
595 	u8		res4[32];
597 	tclayer_t	im_tclayer[8];	/* Eight TCLayers */
598 	u16		tc_tcgsr;
599 	u16		tc_tcger;
603 	u8		res[236];
604 	u32		im_brgc5;
605 	u32		im_brgc6;
606 	u32		im_brgc7;
607 	u32		im_brgc8;
609 	u8		res5[608];
611 	i2c_cpm2_t	im_i2c;		/* I2C control/status */
612 	cpm_cpm2_t	im_cpm;		/* Communication processor */
616 	u32		im_brgc1;
617 	u32		im_brgc2;
618 	u32		im_brgc3;
619 	u32		im_brgc4;
621 	scc_t		im_scc[4];	/* Four SCCs */
622 	smc_t		im_smc[2];	/* Couple of SMCs */
623 	spictl_cpm2_t	im_spi;		/* A SPI */
624 	cpmux_t		im_cpmux;	/* CPM clock route mux */
625 	siramctl_t	im_siramctl1;	/* First SI RAM Control */
626 	mcc_t		im_mcc1;	/* First MCC */
627 	siramctl_t	im_siramctl2;	/* Second SI RAM Control */
628 	mcc_t		im_mcc2;	/* Second MCC */
629 	usb_cpm2_t	im_usb;		/* USB Controller */
631 	u8		res6[1153];
633 	u16		im_si1txram[256];
634 	u8		res7[512];
635 	u16		im_si1rxram[256];
636 	u8		res8[512];
637 	u16		im_si2txram[256];
638 	u8		res9[512];
639 	u16		im_si2rxram[256];
640 	u8		res10[512];
641 	u8		res11[4096];