Lines Matching +full:clock +full:- +full:output +full:- +full:names

36  * different names.  In these cases, one name is chosen to avoid extraneous
44 __be32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */
45 __be32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */
46 __be32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and Control Register */
47 __be32 pordevsr; /* 0x.000c - POR I/O Device Status Register */
48 __be32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */
49 __be32 pordevsr2; /* 0x.0014 - POR device status register 2 */
50 u8 res018[0x20 - 0x18];
51 __be32 porcir; /* 0x.0020 - POR Configuration Information Register */
52 u8 res024[0x30 - 0x24];
53 __be32 gpiocr; /* 0x.0030 - GPIO Control Register */
54 u8 res034[0x40 - 0x34];
55 __be32 gpoutdr; /* 0x.0040 - General-Purpose Output Data Register */
56 u8 res044[0x50 - 0x44];
57 __be32 gpindr; /* 0x.0050 - General-Purpose Input Data Register */
58 u8 res054[0x60 - 0x54];
59 __be32 pmuxcr; /* 0x.0060 - Alternate Function Signal Multiplex Control */
60 __be32 pmuxcr2; /* 0x.0064 - Alternate function signal multiplex control 2 */
61 __be32 dmuxcr; /* 0x.0068 - DMA Mux Control Register */
62 u8 res06c[0x70 - 0x6c];
63 __be32 devdisr; /* 0x.0070 - Device Disable Control */
64 __be32 devdisr2; /* 0x.0074 - Device Disable Control 2 */
65 u8 res078[0x7c - 0x78];
66 __be32 pmjcr; /* 0x.007c - 4 Power Management Jog Control Register */
67 __be32 powmgtcsr; /* 0x.0080 - Power Management Status and Control Register */
68 __be32 pmrccr; /* 0x.0084 - Power Management Reset Counter Configuration Register */
69 __be32 pmpdccr; /* 0x.0088 - Power Management Power Down Counter Configuration Register */
70 __be32 pmcdr; /* 0x.008c - 4Power management clock disable register */
71 __be32 mcpsumr; /* 0x.0090 - Machine Check Summary Register */
72 __be32 rstrscr; /* 0x.0094 - Reset Request Status and Control Register */
73 __be32 ectrstcr; /* 0x.0098 - Exception reset control register */
74 __be32 autorstsr; /* 0x.009c - Automatic reset status register */
75 __be32 pvr; /* 0x.00a0 - Processor Version Register */
76 __be32 svr; /* 0x.00a4 - System Version Register */
77 u8 res0a8[0xb0 - 0xa8];
78 __be32 rstcr; /* 0x.00b0 - Reset Control Register */
79 u8 res0b4[0xc0 - 0xb4];
81 __be32 iovselsr; /* 0x.00c0 - I/O voltage select status register */
83 __be32 elbcvselcr; /* 0x.00c0 - eLBC Voltage Select Ctrl Reg */
85 u8 res0c4[0x224 - 0xc4];
86 __be32 iodelay1; /* 0x.0224 - IO delay control register 1 */
87 __be32 iodelay2; /* 0x.0228 - IO delay control register 2 */
88 u8 res22c[0x800 - 0x22c];
89 __be32 clkdvdr; /* 0x.0800 - Clock Divide Register */
90 u8 res804[0x900 - 0x804];
91 __be32 ircr; /* 0x.0900 - Infrared Control Register */
92 u8 res904[0x908 - 0x904];
93 __be32 dmacr; /* 0x.0908 - DMA Control Register */
94 u8 res90c[0x914 - 0x90c];
95 __be32 elbccr; /* 0x.0914 - eLBC Control Register */
96 u8 res918[0xb20 - 0x918];
97 __be32 ddr1clkdr; /* 0x.0b20 - DDR1 Clock Disable Register */
98 __be32 ddr2clkdr; /* 0x.0b24 - DDR2 Clock Disable Register */
99 __be32 ddrclkdr; /* 0x.0b28 - DDR Clock Disable Register */
100 u8 resb2c[0xe00 - 0xb2c];
101 __be32 clkocr; /* 0x.0e00 - Clock Out Select Register */
102 u8 rese04[0xe10 - 0xe04];
103 __be32 ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */
104 u8 rese14[0xe20 - 0xe14];
105 __be32 lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */
106 __be32 cpfor; /* 0x.0e24 - L2 charge pump fuse override register */
107 u8 rese28[0xf04 - 0xe28];
108 __be32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */
109 __be32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */
110 u8 resf0c[0xf2c - 0xf0c];
111 __be32 itcr; /* 0x.0f2c - Internal transaction control register */
112 u8 resf30[0xf40 - 0xf30];
113 __be32 srds2cr0; /* 0x.0f40 - SerDes2 Control Register 0 */
114 __be32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */
138 unsigned int shift = 16 + (8 * (1 - co) + 2 * (3 - ch)); in guts_set_dmacr()
140 clrsetbits_be32(&guts->dmacr, 3 << shift, device << shift); in guts_set_dmacr()
175 unsigned int shift = 2 * (co + 1) - (ch & 1) - 1; in guts_set_pmuxcr_dma()
177 clrsetbits_be32(&guts->pmuxcr, 1 << shift, value << shift); in guts_set_pmuxcr_dma()