Lines Matching +full:fpga +full:- +full:bridge
12 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
16 compatible = "xlnx,ml510-ref-design", "xlnx,virtex440";
17 dcr-parent = <&ppc440_0>;
28 linux,stdout-path = "/plb@0/serial@83e00000";
31 #address-cells = <1>;
33 #size-cells = <0>;
35 #address-cells = <1>;
36 #size-cells = <1>;
37 clock-frequency = <300000000>;
39 d-cache-line-size = <0x20>;
40 d-cache-size = <0x8000>;
41 dcr-access-method = "native";
42 dcr-controller ;
44 i-cache-line-size = <0x20>;
45 i-cache-size = <0x8000>;
48 timebase-frequency = <300000000>;
49 xlnx,apu-control = <0x2000>;
50 xlnx,apu-udi-0 = <0x0>;
51 xlnx,apu-udi-1 = <0x0>;
52 xlnx,apu-udi-10 = <0x0>;
53 xlnx,apu-udi-11 = <0x0>;
54 xlnx,apu-udi-12 = <0x0>;
55 xlnx,apu-udi-13 = <0x0>;
56 xlnx,apu-udi-14 = <0x0>;
57 xlnx,apu-udi-15 = <0x0>;
58 xlnx,apu-udi-2 = <0x0>;
59 xlnx,apu-udi-3 = <0x0>;
60 xlnx,apu-udi-4 = <0x0>;
61 xlnx,apu-udi-5 = <0x0>;
62 xlnx,apu-udi-6 = <0x0>;
63 xlnx,apu-udi-7 = <0x0>;
64 xlnx,apu-udi-8 = <0x0>;
65 xlnx,apu-udi-9 = <0x0>;
66 xlnx,dcr-autolock-enable = <0x1>;
67 xlnx,dcu-rd-ld-cache-plb-prio = <0x0>;
68 xlnx,dcu-rd-noncache-plb-prio = <0x0>;
69 xlnx,dcu-rd-touch-plb-prio = <0x0>;
70 xlnx,dcu-rd-urgent-plb-prio = <0x0>;
71 xlnx,dcu-wr-flush-plb-prio = <0x0>;
72 xlnx,dcu-wr-store-plb-prio = <0x0>;
73 xlnx,dcu-wr-urgent-plb-prio = <0x0>;
74 xlnx,dma0-control = <0x0>;
75 xlnx,dma0-plb-prio = <0x0>;
76 xlnx,dma0-rxchannelctrl = <0x1010000>;
77 xlnx,dma0-rxirqtimer = <0x3ff>;
78 xlnx,dma0-txchannelctrl = <0x1010000>;
79 xlnx,dma0-txirqtimer = <0x3ff>;
80 xlnx,dma1-control = <0x0>;
81 xlnx,dma1-plb-prio = <0x0>;
82 xlnx,dma1-rxchannelctrl = <0x1010000>;
83 xlnx,dma1-rxirqtimer = <0x3ff>;
84 xlnx,dma1-txchannelctrl = <0x1010000>;
85 xlnx,dma1-txirqtimer = <0x3ff>;
86 xlnx,dma2-control = <0x0>;
87 xlnx,dma2-plb-prio = <0x0>;
88 xlnx,dma2-rxchannelctrl = <0x1010000>;
89 xlnx,dma2-rxirqtimer = <0x3ff>;
90 xlnx,dma2-txchannelctrl = <0x1010000>;
91 xlnx,dma2-txirqtimer = <0x3ff>;
92 xlnx,dma3-control = <0x0>;
93 xlnx,dma3-plb-prio = <0x0>;
94 xlnx,dma3-rxchannelctrl = <0x1010000>;
95 xlnx,dma3-rxirqtimer = <0x3ff>;
96 xlnx,dma3-txchannelctrl = <0x1010000>;
97 xlnx,dma3-txirqtimer = <0x3ff>;
98 xlnx,endian-reset = <0x0>;
99 xlnx,generate-plb-timespecs = <0x1>;
100 xlnx,icu-rd-fetch-plb-prio = <0x0>;
101 xlnx,icu-rd-spec-plb-prio = <0x0>;
102 xlnx,icu-rd-touch-plb-prio = <0x0>;
103 xlnx,interconnect-imask = <0xffffffff>;
104 xlnx,mplb-allow-lock-xfer = <0x1>;
105 xlnx,mplb-arb-mode = <0x0>;
106 xlnx,mplb-awidth = <0x20>;
107 xlnx,mplb-counter = <0x500>;
108 xlnx,mplb-dwidth = <0x80>;
109 xlnx,mplb-max-burst = <0x8>;
110 xlnx,mplb-native-dwidth = <0x80>;
111 xlnx,mplb-p2p = <0x0>;
112 xlnx,mplb-prio-dcur = <0x2>;
113 xlnx,mplb-prio-dcuw = <0x3>;
114 xlnx,mplb-prio-icu = <0x4>;
115 xlnx,mplb-prio-splb0 = <0x1>;
116 xlnx,mplb-prio-splb1 = <0x0>;
117 xlnx,mplb-read-pipe-enable = <0x1>;
118 xlnx,mplb-sync-tattribute = <0x0>;
119 xlnx,mplb-wdog-enable = <0x1>;
120 xlnx,mplb-write-pipe-enable = <0x1>;
121 xlnx,mplb-write-post-enable = <0x1>;
122 xlnx,num-dma = <0x0>;
124 xlnx,ppc440mc-addr-base = <0x0>;
125 xlnx,ppc440mc-addr-high = <0x1fffffff>;
126 xlnx,ppc440mc-arb-mode = <0x0>;
127 xlnx,ppc440mc-bank-conflict-mask = <0x1800000>;
128 xlnx,ppc440mc-control = <0xf810008f>;
129 xlnx,ppc440mc-max-burst = <0x8>;
130 xlnx,ppc440mc-prio-dcur = <0x2>;
131 xlnx,ppc440mc-prio-dcuw = <0x3>;
132 xlnx,ppc440mc-prio-icu = <0x4>;
133 xlnx,ppc440mc-prio-splb0 = <0x1>;
134 xlnx,ppc440mc-prio-splb1 = <0x0>;
135 xlnx,ppc440mc-row-conflict-mask = <0x7ffe00>;
136 xlnx,ppcdm-asyncmode = <0x0>;
137 xlnx,ppcds-asyncmode = <0x0>;
138 xlnx,user-reset = <0x0>;
142 #address-cells = <1>;
143 #size-cells = <1>;
144 compatible = "xlnx,plb-v46-1.03.a", "simple-bus";
147 bank-width = <2>;
148 compatible = "xlnx,xps-mch-emc-2.00.a", "cfi-flash";
151 xlnx,include-datawidth-matching-0 = <0x1>;
152 xlnx,include-datawidth-matching-1 = <0x0>;
153 xlnx,include-datawidth-matching-2 = <0x0>;
154 xlnx,include-datawidth-matching-3 = <0x0>;
155 xlnx,include-negedge-ioregs = <0x0>;
156 xlnx,include-plb-ipif = <0x1>;
157 xlnx,include-wrbuf = <0x1>;
158 xlnx,max-mem-width = <0x10>;
159 xlnx,mch-native-dwidth = <0x20>;
160 xlnx,mch-plb-clk-period-ps = <0x2710>;
161 xlnx,mch-splb-awidth = <0x20>;
162 xlnx,mch0-accessbuf-depth = <0x10>;
163 xlnx,mch0-protocol = <0x0>;
164 xlnx,mch0-rddatabuf-depth = <0x10>;
165 xlnx,mch1-accessbuf-depth = <0x10>;
166 xlnx,mch1-protocol = <0x0>;
167 xlnx,mch1-rddatabuf-depth = <0x10>;
168 xlnx,mch2-accessbuf-depth = <0x10>;
169 xlnx,mch2-protocol = <0x0>;
170 xlnx,mch2-rddatabuf-depth = <0x10>;
171 xlnx,mch3-accessbuf-depth = <0x10>;
172 xlnx,mch3-protocol = <0x0>;
173 xlnx,mch3-rddatabuf-depth = <0x10>;
174 xlnx,mem0-width = <0x10>;
175 xlnx,mem1-width = <0x20>;
176 xlnx,mem2-width = <0x20>;
177 xlnx,mem3-width = <0x20>;
178 xlnx,num-banks-mem = <0x1>;
179 xlnx,num-channels = <0x2>;
180 xlnx,priority-mode = <0x0>;
181 xlnx,synch-mem-0 = <0x0>;
182 xlnx,synch-mem-1 = <0x0>;
183 xlnx,synch-mem-2 = <0x0>;
184 xlnx,synch-mem-3 = <0x0>;
185 xlnx,synch-pipedelay-0 = <0x2>;
186 xlnx,synch-pipedelay-1 = <0x2>;
187 xlnx,synch-pipedelay-2 = <0x2>;
188 xlnx,synch-pipedelay-3 = <0x2>;
189 xlnx,tavdv-ps-mem-0 = <0x1adb0>;
190 xlnx,tavdv-ps-mem-1 = <0x3a98>;
191 xlnx,tavdv-ps-mem-2 = <0x3a98>;
192 xlnx,tavdv-ps-mem-3 = <0x3a98>;
193 xlnx,tcedv-ps-mem-0 = <0x1adb0>;
194 xlnx,tcedv-ps-mem-1 = <0x3a98>;
195 xlnx,tcedv-ps-mem-2 = <0x3a98>;
196 xlnx,tcedv-ps-mem-3 = <0x3a98>;
197 xlnx,thzce-ps-mem-0 = <0x88b8>;
198 xlnx,thzce-ps-mem-1 = <0x1b58>;
199 xlnx,thzce-ps-mem-2 = <0x1b58>;
200 xlnx,thzce-ps-mem-3 = <0x1b58>;
201 xlnx,thzoe-ps-mem-0 = <0x1b58>;
202 xlnx,thzoe-ps-mem-1 = <0x1b58>;
203 xlnx,thzoe-ps-mem-2 = <0x1b58>;
204 xlnx,thzoe-ps-mem-3 = <0x1b58>;
205 xlnx,tlzwe-ps-mem-0 = <0x88b8>;
206 xlnx,tlzwe-ps-mem-1 = <0x0>;
207 xlnx,tlzwe-ps-mem-2 = <0x0>;
208 xlnx,tlzwe-ps-mem-3 = <0x0>;
209 xlnx,twc-ps-mem-0 = <0x1adb0>;
210 xlnx,twc-ps-mem-1 = <0x3a98>;
211 xlnx,twc-ps-mem-2 = <0x3a98>;
212 xlnx,twc-ps-mem-3 = <0x3a98>;
213 xlnx,twp-ps-mem-0 = <0x11170>;
214 xlnx,twp-ps-mem-1 = <0x2ee0>;
215 xlnx,twp-ps-mem-2 = <0x2ee0>;
216 xlnx,twp-ps-mem-3 = <0x2ee0>;
217 xlnx,xcl0-linesize = <0x4>;
218 xlnx,xcl0-writexfer = <0x1>;
219 xlnx,xcl1-linesize = <0x4>;
220 xlnx,xcl1-writexfer = <0x1>;
221 xlnx,xcl2-linesize = <0x4>;
222 xlnx,xcl2-writexfer = <0x1>;
223 xlnx,xcl3-linesize = <0x4>;
224 xlnx,xcl3-writexfer = <0x1>;
226 Hard_Ethernet_MAC: xps-ll-temac@81c00000 {
227 #address-cells = <1>;
228 #size-cells = <1>;
231 compatible = "xlnx,xps-ll-temac-1.01.b";
233 interrupt-parent = <&xps_intc_0>;
235 llink-connected = <&Hard_Ethernet_MAC_fifo>;
236 local-mac-address = [ 02 00 00 00 00 00 ];
238 xlnx,bus2core-clk-ratio = <0x1>;
239 xlnx,phy-type = <0x3>;
243 xlnx,temac-type = <0x0>;
248 Hard_Ethernet_MAC_fifo: xps-ll-fifo@81a00000 {
249 compatible = "xlnx,xps-ll-fifo-1.01.a";
250 interrupt-parent = <&xps_intc_0>;
256 compatible = "xlnx,xps-iic-2.00.a";
257 interrupt-parent = <&xps_intc_0>;
260 xlnx,clk-freq = <0x5f5e100>;
262 xlnx,gpo-width = <0x1>;
263 xlnx,iic-freq = <0x186a0>;
264 xlnx,scl-inertial-delay = <0x5>;
265 xlnx,sda-inertial-delay = <0x5>;
266 xlnx,ten-bit-adr = <0x0>;
269 compatible = "xlnx,xps-gpio-1.00.a";
271 xlnx,all-inputs = <0x0>;
272 xlnx,all-inputs-2 = <0x0>;
273 xlnx,dout-default = <0x0>;
274 xlnx,dout-default-2 = <0x0>;
276 xlnx,gpio-width = <0xb>;
277 xlnx,interrupt-present = <0x0>;
278 xlnx,is-bidir = <0x1>;
279 xlnx,is-bidir-2 = <0x1>;
280 xlnx,is-dual = <0x0>;
281 xlnx,tri-default = <0xffffffff>;
282 xlnx,tri-default-2 = <0xffffffff>;
285 compatible = "xlnx,xps-gpio-1.00.a";
287 xlnx,all-inputs = <0x0>;
288 xlnx,all-inputs-2 = <0x0>;
289 xlnx,dout-default = <0x0>;
290 xlnx,dout-default-2 = <0x0>;
292 xlnx,gpio-width = <0x4>;
293 xlnx,interrupt-present = <0x0>;
294 xlnx,is-bidir = <0x1>;
295 xlnx,is-bidir-2 = <0x1>;
296 xlnx,is-dual = <0x0>;
297 xlnx,tri-default = <0xffffffff>;
298 xlnx,tri-default-2 = <0xffffffff>;
301 clock-frequency = <100000000>;
302 compatible = "xlnx,xps-uart16550-2.00.b", "ns16550";
303 current-speed = <9600>;
305 interrupt-parent = <&xps_intc_0>;
308 reg-offset = <0x1003>;
309 reg-shift = <2>;
311 xlnx,has-external-rclk = <0x0>;
312 xlnx,has-external-xin = <0x0>;
313 xlnx,is-a-16550 = <0x1>;
315 SPI_EEPROM: xps-spi@feff8000 {
316 compatible = "xlnx,xps-spi-2.00.b";
317 interrupt-parent = <&xps_intc_0>;
321 xlnx,fifo-exist = <0x1>;
322 xlnx,num-ss-bits = <0x1>;
323 xlnx,num-transfer-bits = <0x8>;
324 xlnx,sck-ratio = <0x80>;
327 compatible = "xlnx,xps-sysace-1.00.a";
328 interrupt-parent = <&xps_intc_0>;
332 xlnx,mem-width = <0x10>;
334 plbv46_pci_0: plbv46-pci@85e00000 {
335 #size-cells = <2>;
336 #address-cells = <3>;
337 compatible = "xlnx,plbv46-pci-1.03.a";
353 #interrupt-cells = <1>;
354 interrupt-parent = <&xps_intc_0>;
355 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
356 interrupt-map = <
363 * connected to the south bridge and this one
389 * ABCD [FPGA] of slot 5 is mapped to DABC.
421 #size-cells = <1>;
422 #address-cells = <2>;
423 i8259: interrupt-controller@20 {
427 interrupt-controller;
428 device_type = "interrupt-controller";
429 #address-cells = <0>;
430 #interrupt-cells = <2>;
433 /* south bridge irq is active high */
435 interrupt-parent = <&xps_intc_0>;
439 xps_bram_if_cntlr_1: xps-bram-if-cntlr@ffff0000 {
440 compatible = "xlnx,xps-bram-if-cntlr-1.00.a";
444 xps_intc_0: interrupt-controller@81800000 {
445 #interrupt-cells = <0x2>;
446 compatible = "xlnx,xps-intc-1.00.a";
447 interrupt-controller ;
449 xlnx,num-intr-inputs = <0xc>;
452 compatible = "xlnx,xps-tft-1.00.a";
454 xlnx,dcr-splb-slave-if = <0x1>;
455 xlnx,default-tft-base-addr = <0x0>;
457 xlnx,i2c-slave-addr = <0x76>;
458 xlnx,mplb-awidth = <0x20>;
459 xlnx,mplb-dwidth = <0x80>;
460 xlnx,mplb-native-dwidth = <0x40>;
461 xlnx,mplb-smallest-slave = <0x20>;
462 xlnx,tft-interface = <0x1>;