boot/dts/p2020ds.dtsi

2  * P2020DS Device Tree Source stub (no addresses or top-level ranges)
4  * Copyright 2011-2012 Freescale Semiconductor Inc.
14  *       names of its contributors may be used to endorse or promote products
37 		#address-cells = <1>;
38 		#size-cells = <1>;
39 		compatible = "cfi-flash";
40 		reg = <0x0 0x0 0x8000000>;
41 		bank-width = <2>;
42 		device-width = <1>;
45 			reg = <0x0 0x03000000>;
46 			read-only;
50 			reg = <0x03000000 0x00e00000>;
51 			read-only;
55 			reg = <0x03e00000 0x00200000>;
56 			read-only;
60 			reg = <0x04000000 0x00400000>;
61 			read-only;
65 			reg = <0x04400000 0x03b00000>;
69 			reg = <0x07f00000 0x00080000>;
70 			read-only;
73 		u-boot@7f80000 {
74 			reg = <0x07f80000 0x00080000>;
75 			read-only;
80 		#address-cells = <1>;
81 		#size-cells = <1>;
82 		compatible = "fsl,elbc-fcm-nand";
83 		reg = <0x2 0x0 0x40000>;
85 		u-boot@0 {
86 			reg = <0x0 0x02000000>;
87 			read-only;
91 			reg = <0x02000000 0x10000000>;
95 			reg = <0x12000000 0x08000000>;
96 			read-only;
100 			reg = <0x1a000000 0x04000000>;
104 			reg = <0x1e000000 0x01000000>;
105 			read-only;
109 			reg = <0x1f000000 0x21000000>;
113 	board-control@3,0 {
114 		compatible = "fsl,p2020ds-fpga", "fsl,fpga-ngpixis";
115 		reg = <0x3 0x0 0x30>;
119 		compatible = "fsl,elbc-fcm-nand";
120 		reg = <0x4 0x0 0x40000>;
124 		compatible = "fsl,elbc-fcm-nand";
125 		reg = <0x5 0x0 0x40000>;
129 		compatible = "fsl,elbc-fcm-nand";
130 		reg = <0x6 0x0 0x40000>;
141 		phy0: ethernet-phy@0 {
143 			reg = <0x0>;
145 		phy1: ethernet-phy@1 {
147 			reg = <0x1>;
149 		phy2: ethernet-phy@2 {
151 			reg = <0x2>;
153 		tbi0: tbi-phy@11 {
154 			reg = <0x11>;
155 			device_type = "tbi-phy";
161 		tbi1: tbi-phy@11 {
162 			reg = <0x11>;
163 			device_type = "tbi-phy";
168 		tbi2: tbi-phy@11 {
169 			reg = <0x11>;
170 			device_type = "tbi-phy";
176 		fsl,tclk-period = <5>;
177 		fsl,tmr-prsc = <200>;
178 		fsl,tmr-add = <0xCCCCCCCD>;
179 		fsl,tmr-fiper1 = <0x3B9AC9FB>;
180 		fsl,tmr-fiper2 = <0x0001869B>;
181 		fsl,max-adj = <249999999>;
185 		tbi-handle = <&tbi0>;
186 		phy-handle = <&phy0>;
187 		phy-connection-type = "rgmii-id";
191 		tbi-handle = <&tbi1>;
192 		phy-handle = <&phy1>;
193 		phy-connection-type = "rgmii-id";
198 		tbi-handle = <&tbi2>;
199 		phy-handle = <&phy2>;
200 		phy-connection-type = "rgmii-id";
206 		interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
207 		interrupt-map = <
209 			// IDSEL 0x11 func 0 - PCI slot 1
213 			// IDSEL 0x11 func 1 - PCI slot 1
217 			// IDSEL 0x11 func 2 - PCI slot 1
221 			// IDSEL 0x11 func 3 - PCI slot 1
225 			// IDSEL 0x11 func 4 - PCI slot 1
229 			// IDSEL 0x11 func 5 - PCI slot 1
233 			// IDSEL 0x11 func 6 - PCI slot 1
237 			// IDSEL 0x11 func 7 - PCI slot 1
254 			reg = <0x0 0x0 0x0 0x0 0x0>;
255 			#size-cells = <2>;
256 			#address-cells = <3>;
266 				#interrupt-cells = <2>;
267 				#size-cells = <1>;
268 				#address-cells = <2>;
269 				reg = <0xf000 0x0 0x0 0x0 0x0>;
272 				interrupt-parent = <&i8259>;
274 				i8259: interrupt-controller@20 {
275 					reg = <0x1 0x20 0x2
278 					interrupt-controller;
279 					device_type = "interrupt-controller";
280 					#address-cells = <0>;
281 					#interrupt-cells = <2>;
284 					interrupt-parent = <&mpic>;
288 					#size-cells = <0>;
289 					#address-cells = <1>;
290 					reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
292 					interrupt-parent =
296 						reg = <0x0>;
301 						reg = <0x1>;
308 					reg = <0x1 0x70 0x2>;
312 					reg = <0x1 0x400 0x80>;