Lines Matching +full:reg +full:- +full:names
2 * MPC8572DS Device Tree Source stub (no addresses or top-level ranges)
14 * names of its contributors may be used to endorse or promote products
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
40 reg = <0x0 0x0 0x8000000>;
41 bank-width = <2>;
42 device-width = <1>;
45 reg = <0x0 0x03000000>;
46 read-only;
50 reg = <0x03000000 0x00e00000>;
51 read-only;
55 reg = <0x03e00000 0x00200000>;
56 read-only;
60 reg = <0x04000000 0x00400000>;
61 read-only;
65 reg = <0x04400000 0x03b00000>;
69 reg = <0x07f00000 0x00080000>;
70 read-only;
73 u-boot@7f80000 {
74 reg = <0x07f80000 0x00080000>;
75 read-only;
80 #address-cells = <1>;
81 #size-cells = <1>;
82 compatible = "fsl,mpc8572-fcm-nand",
83 "fsl,elbc-fcm-nand";
84 reg = <0x2 0x0 0x40000>;
86 u-boot@0 {
87 reg = <0x0 0x02000000>;
88 read-only;
92 reg = <0x02000000 0x10000000>;
96 reg = <0x12000000 0x08000000>;
97 read-only;
101 reg = <0x1a000000 0x04000000>;
105 reg = <0x1e000000 0x01000000>;
106 read-only;
110 reg = <0x1f000000 0x21000000>;
115 compatible = "fsl,mpc8572-fcm-nand",
116 "fsl,elbc-fcm-nand";
117 reg = <0x4 0x0 0x40000>;
121 compatible = "fsl,mpc8572-fcm-nand",
122 "fsl,elbc-fcm-nand";
123 reg = <0x5 0x0 0x40000>;
127 compatible = "fsl,mpc8572-fcm-nand",
128 "fsl,elbc-fcm-nand";
129 reg = <0x6 0x0 0x40000>;
135 tbi-handle = <&tbi0>;
136 phy-handle = <&phy0>;
137 phy-connection-type = "rgmii-id";
141 phy0: ethernet-phy@0 {
143 reg = <0x0>;
145 phy1: ethernet-phy@1 {
147 reg = <0x1>;
149 phy2: ethernet-phy@2 {
151 reg = <0x2>;
153 phy3: ethernet-phy@3 {
155 reg = <0x3>;
158 tbi0: tbi-phy@11 {
159 reg = <0x11>;
160 device_type = "tbi-phy";
165 fsl,tclk-period = <5>;
166 fsl,tmr-prsc = <200>;
167 fsl,tmr-add = <0xAAAAAAAB>;
168 fsl,tmr-fiper1 = <0x3B9AC9FB>;
169 fsl,tmr-fiper2 = <0x3B9AC9FB>;
170 fsl,max-adj = <499999999>;
174 tbi-handle = <&tbi1>;
175 phy-handle = <&phy1>;
176 phy-connection-type = "rgmii-id";
181 tbi1: tbi-phy@11 {
182 reg = <0x11>;
183 device_type = "tbi-phy";
188 tbi-handle = <&tbi2>;
189 phy-handle = <&phy2>;
190 phy-connection-type = "rgmii-id";
194 tbi2: tbi-phy@11 {
195 reg = <0x11>;
196 device_type = "tbi-phy";
201 tbi-handle = <&tbi3>;
202 phy-handle = <&phy3>;
203 phy-connection-type = "rgmii-id";
207 tbi3: tbi-phy@11 {
208 reg = <0x11>;
209 device_type = "tbi-phy";
216 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
217 interrupt-map = <
218 /* IDSEL 0x11 func 0 - PCI slot 1 */
224 /* IDSEL 0x11 func 1 - PCI slot 1 */
230 /* IDSEL 0x11 func 2 - PCI slot 1 */
236 /* IDSEL 0x11 func 3 - PCI slot 1 */
242 /* IDSEL 0x11 func 4 - PCI slot 1 */
248 /* IDSEL 0x11 func 5 - PCI slot 1 */
254 /* IDSEL 0x11 func 6 - PCI slot 1 */
260 /* IDSEL 0x11 func 7 - PCI slot 1 */
266 /* IDSEL 0x12 func 0 - PCI slot 2 */
272 /* IDSEL 0x12 func 1 - PCI slot 2 */
278 /* IDSEL 0x12 func 2 - PCI slot 2 */
284 /* IDSEL 0x12 func 3 - PCI slot 2 */
290 /* IDSEL 0x12 func 4 - PCI slot 2 */
296 /* IDSEL 0x12 func 5 - PCI slot 2 */
302 /* IDSEL 0x12 func 6 - PCI slot 2 */
308 /* IDSEL 0x12 func 7 - PCI slot 2 */
334 reg = <0x0 0x0 0x0 0x0 0x0>;
335 #size-cells = <2>;
336 #address-cells = <3>;
346 #interrupt-cells = <2>;
347 #size-cells = <1>;
348 #address-cells = <2>;
349 reg = <0xf000 0x0 0x0 0x0 0x0>;
352 interrupt-parent = <&i8259>;
354 i8259: interrupt-controller@20 {
355 reg = <0x1 0x20 0x2
358 interrupt-controller;
359 device_type = "interrupt-controller";
360 #address-cells = <0>;
361 #interrupt-cells = <2>;
364 interrupt-parent = <&mpic>;
368 #size-cells = <0>;
369 #address-cells = <1>;
370 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
372 interrupt-parent =
376 reg = <0x0>;
381 reg = <0x1>;
388 reg = <0x1 0x70 0x2>;
392 reg = <0x1 0x400 0x80>;