boot/dts/mpc8377_wlan.dts

4  * Copyright 2007-2009 Freescale Semiconductor Inc.
13 /dts-v1/;
17 	#address-cells = <1>;
18 	#size-cells = <1>;
31 		#address-cells = <1>;
32 		#size-cells = <0>;
37 			d-cache-line-size = <32>;
38 			i-cache-line-size = <32>;
39 			d-cache-size = <32768>;
40 			i-cache-size = <32768>;
41 			timebase-frequency = <0>;
42 			bus-frequency = <0>;
43 			clock-frequency = <0>;
53 		#address-cells = <2>;
54 		#size-cells = <1>;
55 		compatible = "fsl,mpc8377-elbc", "fsl,elbc", "simple-bus";
58 		interrupt-parent = <&ipic>;
62 			#address-cells = <1>;
63 			#size-cells = <1>;
64 			compatible = "cfi-flash";
66 			bank-width = <2>;
67 			device-width = <1>;
71 				label = "u-boot";
72 				read-only;
88 		#address-cells = <1>;
89 		#size-cells = <1>;
91 		compatible = "simple-bus";
94 		bus-frequency = <0>;
102 		gpio1: gpio-controller@c00 {
103 			#gpio-cells = <2>;
104 			compatible = "fsl,mpc8377-gpio", "fsl,mpc8349-gpio";
107 			interrupt-parent = <&ipic>;
108 			gpio-controller;
111 		gpio2: gpio-controller@d00 {
112 			#gpio-cells = <2>;
113 			compatible = "fsl,mpc8377-gpio", "fsl,mpc8349-gpio";
116 			interrupt-parent = <&ipic>;
117 			gpio-controller;
120 		sleep-nexus {
121 			#address-cells = <1>;
122 			#size-cells = <1>;
123 			compatible = "simple-bus";
128 				#address-cells = <1>;
129 				#size-cells = <0>;
130 				cell-index = <0>;
131 				compatible = "fsl-i2c";
134 				interrupt-parent = <&ipic>;
149 				compatible = "fsl,mpc8377-esdhc", "fsl,esdhc";
152 				interrupt-parent = <&ipic>;
153 				sdhci,wp-inverted;
154 				clock-frequency = <133333333>;
159 			#address-cells = <1>;
160 			#size-cells = <0>;
161 			cell-index = <1>;
162 			compatible = "fsl-i2c";
165 			interrupt-parent = <&ipic>;
170 			cell-index = <0>;
174 			interrupt-parent = <&ipic>;
179 			#address-cells = <1>;
180 			#size-cells = <1>;
181 			compatible = "fsl,mpc8377-dma", "fsl,elo-dma";
184 			interrupt-parent = <&ipic>;
186 			cell-index = <0>;
187 			dma-channel@0 {
188 				compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
190 				cell-index = <0>;
191 				interrupt-parent = <&ipic>;
194 			dma-channel@80 {
195 				compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
197 				cell-index = <1>;
198 				interrupt-parent = <&ipic>;
201 			dma-channel@100 {
202 				compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
204 				cell-index = <2>;
205 				interrupt-parent = <&ipic>;
208 			dma-channel@180 {
209 				compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
211 				cell-index = <3>;
212 				interrupt-parent = <&ipic>;
218 			compatible = "fsl-usb2-dr";
220 			#address-cells = <1>;
221 			#size-cells = <0>;
222 			interrupt-parent = <&ipic>;
229 			#address-cells = <1>;
230 			#size-cells = <1>;
231 			cell-index = <0>;
237 			local-mac-address = [ 00 00 00 00 00 00 ];
239 			phy-connection-type = "mii";
240 			interrupt-parent = <&ipic>;
241 			tbi-handle = <&tbi0>;
242 			phy-handle = <&phy2>;
244 			fsl,magic-packet;
247 				#address-cells = <1>;
248 				#size-cells = <0>;
249 				compatible = "fsl,gianfar-mdio";
252 				phy2: ethernet-phy@2 {
253 					interrupt-parent = <&ipic>;
256 					device_type = "ethernet-phy";
259 				phy3: ethernet-phy@3 {
260 					interrupt-parent = <&ipic>;
263 					device_type = "ethernet-phy";
266 				tbi0: tbi-phy@11 {
268 					device_type = "tbi-phy";
274 			#address-cells = <1>;
275 			#size-cells = <1>;
276 			cell-index = <1>;
282 			local-mac-address = [ 00 00 00 00 00 00 ];
284 			phy-connection-type = "mii";
285 			interrupt-parent = <&ipic>;
286 			phy-handle = <&phy3>;
287 			tbi-handle = <&tbi1>;
289 			fsl,magic-packet;
292 				#address-cells = <1>;
293 				#size-cells = <0>;
294 				compatible = "fsl,gianfar-tbi";
297 				tbi1: tbi-phy@11 {
299 					device_type = "tbi-phy";
305 			cell-index = <0>;
309 			clock-frequency = <0>;
311 			interrupt-parent = <&ipic>;
315 			cell-index = <1>;
319 			clock-frequency = <0>;
321 			interrupt-parent = <&ipic>;
329 			interrupt-parent = <&ipic>;
330 			fsl,num-channels = <4>;
331 			fsl,channel-fifo-len = <24>;
332 			fsl,exec-units-mask = <0x9fe>;
333 			fsl,descriptor-types-mask = <0x3ab0ebf>;
338 			compatible = "fsl,mpc8377-sata", "fsl,pq-sata";
341 			interrupt-parent = <&ipic>;
346 			compatible = "fsl,mpc8377-sata", "fsl,pq-sata";
349 			interrupt-parent = <&ipic>;
357 		 * sense == 2: Edge, high-to-low change
359 		ipic: interrupt-controller@700 {
361 			interrupt-controller;
362 			#address-cells = <0>;
363 			#interrupt-cells = <2>;
368 			compatible = "fsl,mpc8377-pmc", "fsl,mpc8349-pmc";
371 			interrupt-parent = <&ipic>;
376 		interrupt-map-mask = <0xf800 0 0 7>;
377 		interrupt-map = <
385 		interrupt-parent = <&ipic>;
387 		bus-range = <0 0>;
392 		clock-frequency = <66666666>;
393 		#interrupt-cells = <1>;
394 		#size-cells = <2>;
395 		#address-cells = <3>;
398 		compatible = "fsl,mpc8349-pci";
403 		#address-cells = <3>;
404 		#size-cells = <2>;
405 		#interrupt-cells = <1>;
407 		compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
411 		bus-range = <0 255>;
412 		interrupt-map-mask = <0xf800 0 0 7>;
413 		interrupt-map = <0 0 0 1 &ipic 1 8
418 		clock-frequency = <0>;
421 			#address-cells = <3>;
422 			#size-cells = <2>;
435 		#address-cells = <3>;
436 		#size-cells = <2>;
437 		#interrupt-cells = <1>;
439 		compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
443 		bus-range = <0 255>;
444 		interrupt-map-mask = <0xf800 0 0 7>;
445 		interrupt-map = <0 0 0 1 &ipic 2 8
450 		clock-frequency = <0>;
453 			#address-cells = <3>;
454 			#size-cells = <2>;