Lines Matching +full:spi +full:- +full:tx +full:- +full:bus +full:- +full:width
5 * Copyright 2007-2008 MontaVista Software, Inc.
15 /dts-v1/;
18 #address-cells = <1>;
19 #size-cells = <1>;
35 #address-cells = <1>;
36 #size-cells = <0>;
41 d-cache-line-size = <32>;
42 i-cache-line-size = <32>;
43 d-cache-size = <32768>;
44 i-cache-size = <32768>;
45 /* filled by u-boot */
46 timebase-frequency = <0>;
47 bus-frequency = <0>;
48 clock-frequency = <0>;
54 /* filled by u-boot */
59 #address-cells = <1>;
60 #size-cells = <1>;
62 compatible = "fsl,mpc8360-immr", "fsl,immr", "fsl,soc",
63 "simple-bus";
66 /* filled by u-boot */
67 bus-frequency = <0>;
75 compatible = "fsl,mpc8360-pmc", "fsl,mpc8349-pmc";
78 interrupt-parent = <&ipic>;
82 #address-cells = <1>;
83 #size-cells = <0>;
84 cell-index = <0>;
85 compatible = "fsl-i2c";
88 interrupt-parent = <&ipic>;
93 #address-cells = <1>;
94 #size-cells = <0>;
95 cell-index = <1>;
96 compatible = "fsl-i2c";
99 interrupt-parent = <&ipic>;
108 interrupt-parent = <&ipic>;
109 /* filled by u-boot */
110 clock-frequency = <0>;
118 interrupt-parent = <&ipic>;
119 /* filled by u-boot */
120 clock-frequency = <0>;
124 #address-cells = <1>;
125 #size-cells = <1>;
126 compatible = "fsl,mpc8360-dma", "fsl,elo-dma";
129 interrupt-parent = <&ipic>;
131 cell-index = <0>;
132 dma-channel@0 {
133 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
135 cell-index = <0>;
136 interrupt-parent = <&ipic>;
139 dma-channel@80 {
140 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
142 cell-index = <1>;
143 interrupt-parent = <&ipic>;
146 dma-channel@100 {
147 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
149 cell-index = <2>;
150 interrupt-parent = <&ipic>;
153 dma-channel@180 {
154 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
156 cell-index = <3>;
157 interrupt-parent = <&ipic>;
166 interrupt-parent = <&ipic>;
167 fsl,num-channels = <4>;
168 fsl,channel-fifo-len = <24>;
169 fsl,exec-units-mask = <0x7e>;
170 fsl,descriptor-types-mask = <0x01010ebf>;
174 ipic: interrupt-controller@700 {
175 #address-cells = <0>;
176 #interrupt-cells = <2>;
177 compatible = "fsl,pq2pro-pic", "fsl,ipic";
178 interrupt-controller;
182 qe_pio_b: gpio-controller@1418 {
183 #gpio-cells = <2>;
184 compatible = "fsl,mpc8360-qe-pario-bank",
185 "fsl,mpc8323-qe-pario-bank";
187 gpio-controller;
190 qe_pio_e: gpio-controller@1460 {
191 #gpio-cells = <2>;
192 compatible = "fsl,mpc8360-qe-pario-bank",
193 "fsl,mpc8323-qe-pario-bank";
195 gpio-controller;
199 #address-cells = <1>;
200 #size-cells = <1>;
202 compatible = "fsl,qe", "simple-bus";
205 /* filled by u-boot */
206 clock-frequency = <0>;
207 bus-frequency = <0>;
208 brg-frequency = <0>;
209 fsl,qe-num-riscs = <2>;
210 fsl,qe-num-snums = <28>;
213 #address-cells = <1>;
214 #size-cells = <1>;
215 compatible = "fsl,qe-muram", "fsl,cpm-muram";
218 data-only@0 {
219 compatible = "fsl,qe-muram-data",
220 "fsl,cpm-muram-data";
226 compatible = "fsl,mpc8360-qe-gtm",
227 "fsl,qe-gtm", "fsl,gtm";
230 interrupt-parent = <&qeic>;
231 clock-frequency = <166666666>;
235 compatible = "fsl,mpc8360-qe-usb",
236 "fsl,mpc8323-qe-usb";
239 interrupt-parent = <&qeic>;
240 fsl,fullspeed-clock = "clk21";
250 spi@4c0 {
251 cell-index = <0>;
252 compatible = "fsl,spi";
255 interrupt-parent = <&qeic>;
256 mode = "cpu-qe";
259 spi@500 {
260 cell-index = <1>;
261 compatible = "fsl,spi";
264 interrupt-parent = <&qeic>;
265 mode = "cpu-qe";
271 cell-index = <1>;
274 interrupt-parent = <&qeic>;
275 rx-clock-name = "none";
276 tx-clock-name = "clk9";
277 phy-handle = <&phy2>;
278 phy-connection-type = "rgmii-rxid";
279 /* filled by u-boot */
280 local-mac-address = [ 00 00 00 00 00 00 ];
286 cell-index = <2>;
289 interrupt-parent = <&qeic>;
290 rx-clock-name = "none";
291 tx-clock-name = "clk4";
292 phy-handle = <&phy4>;
293 phy-connection-type = "rgmii-rxid";
294 /* filled by u-boot */
295 local-mac-address = [ 00 00 00 00 00 00 ];
301 cell-index = <7>;
304 interrupt-parent = <&qeic>;
305 rx-clock-name = "clk20";
306 tx-clock-name = "clk19";
307 phy-handle = <&phy1>;
308 phy-connection-type = "mii";
309 /* filled by u-boot */
310 local-mac-address = [ 00 00 00 00 00 00 ];
316 cell-index = <4>;
319 interrupt-parent = <&qeic>;
320 rx-clock-name = "clk8";
321 tx-clock-name = "clk7";
322 phy-handle = <&phy3>;
323 phy-connection-type = "mii";
324 /* filled by u-boot */
325 local-mac-address = [ 00 00 00 00 00 00 ];
329 #address-cells = <1>;
330 #size-cells = <0>;
331 compatible = "fsl,ucc-mdio";
334 phy1: ethernet-phy@1 {
335 device_type = "ethernet-phy";
340 phy2: ethernet-phy@2 {
341 device_type = "ethernet-phy";
346 phy3: ethernet-phy@3 {
347 device_type = "ethernet-phy";
352 phy4: ethernet-phy@4 {
353 device_type = "ethernet-phy";
363 cell-index = <5>;
364 port-number = <0>;
365 rx-clock-name = "brg7";
366 tx-clock-name = "brg8";
368 interrupt-parent = <&qeic>;
369 soft-uart;
376 cell-index = <6>;
377 port-number = <1>;
378 rx-clock-name = "brg13";
379 tx-clock-name = "brg14";
381 interrupt-parent = <&qeic>;
382 soft-uart;
385 qeic: interrupt-controller@80 {
386 #address-cells = <0>;
387 #interrupt-cells = <1>;
388 compatible = "fsl,qe-ic";
389 interrupt-controller;
391 big-endian;
393 interrupt-parent = <&ipic>;
399 #address-cells = <2>;
400 #size-cells = <1>;
401 compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus",
402 "simple-bus";
409 compatible = "intel,PC28F640P30T85", "cfi-flash";
411 bank-width = <2>;
412 device-width = <1>;
416 compatible = "fsl,upm-nand";
418 fsl,upm-addr-offset = <16>;
419 fsl,upm-cmd-offset = <8>;
423 compatible = "stm,nand512-a";
432 little-endian;
433 /* filled by u-boot */
436 width = <0>;
439 /* linux,opened; - added by uboot */
444 #address-cells = <3>;
445 #size-cells = <2>;
446 #interrupt-cells = <1>;
448 compatible = "fsl,mpc8360-pci", "fsl,mpc8349-pci";
455 interrupt-parent = <&ipic>;
456 interrupt-map-mask = <0xf800 0 0 7>;
457 interrupt-map = </* miniPCI0 IDSEL 0x14 AD20 */
467 /* filled by u-boot */
468 bus-range = <0 0>;
469 clock-frequency = <0>;