Lines Matching +full:0 +full:x00400000
40 #size-cells = <0>;
42 PowerPC,8641@0 {
44 reg = <0>;
49 timebase-frequency = <0>; // From uboot
50 bus-frequency = <0>; // From uboot
51 clock-frequency = <0>; // From uboot
60 timebase-frequency = <0>; // From uboot
61 bus-frequency = <0>; // From uboot
62 clock-frequency = <0>; // From uboot
68 reg = <0x0 0x40000000>; // set by uboot
75 reg = <0xfef05000 0x1000>;
79 ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
80 1 0 0xe0000000 0x08000000 // Paged Flash 0
81 2 0 0xe8000000 0x08000000 // Paged Flash 1
82 3 0 0xfc100000 0x00020000 // NVRAM
83 4 0 0xfc000000 0x00010000>; // FPGA
85 /* flash@0,0 is a mirror of part of the memory in flash@1,0
86 flash@0,0 {
88 reg = <0x0 0x0 0x01000000>;
93 partition@0 {
95 reg = <0x0 0x01000000>;
101 flash@1,0 {
103 reg = <0x1 0x0 0x8000000>;
108 partition@0 {
110 reg = <0x0 0x7800000>;
114 reg = <0x7800000 0x800000>;
119 nvram@3,0 {
122 reg = <0x3 0x0 0x20000>;
125 fpga@4,0 {
127 reg = <0x4 0x0 0x40>;
133 reg = <0x4 0x2000 0x8>;
134 interrupts = <0x1a 0x4>;
141 reg = <0x4 0x2010 0x8>;
142 interrupts = <0x1b 0x4>;
150 reg = <0x4 0x4000 0x20>;
151 interrupts = <0x8
152 0x9>;
159 reg = <0x4 0x8000 0x24>;
170 ranges = <0x0 0xfef00000 0x00100000>;
173 mcm-law@0 {
175 reg = <0x0 0x1000>;
181 reg = <0x1000 0x1000>;
188 #size-cells = <0>;
190 reg = <0x3000 0x100>;
191 interrupts = <0x2b 0x2>;
197 reg = <0x00000051>;
203 #size-cells = <0>;
205 reg = <0x3100 0x100>;
206 interrupts = <0x2b 0x2>;
212 reg = <0x48>;
217 reg = <0x4c>;
222 reg = <0x6b>;
230 reg = <0x21300 0x4>;
231 ranges = <0x0 0x21100 0x200>;
232 cell-index = <0>;
233 dma-channel@0 {
236 reg = <0x0 0x80>;
237 cell-index = <0>;
244 reg = <0x80 0x80>;
252 reg = <0x100 0x80>;
260 reg = <0x180 0x80>;
270 cell-index = <0>;
274 reg = <0x24000 0x1000>;
275 ranges = <0x0 0x24000 0x1000>;
285 #size-cells = <0>;
287 reg = <0x520 0x20>;
289 phy0: ethernet-phy@0 {
291 interrupts = <0x9 0x4>;
297 interrupts = <0x8 0x4>;
302 reg = <0x11>;
315 reg = <0x26000 0x1000>;
316 ranges = <0x0 0x26000 0x1000>;
326 #size-cells = <0>;
328 reg = <0x520 0x20>;
331 reg = <0x11>;
338 cell-index = <0>;
341 reg = <0x4500 0x100>;
342 clock-frequency = <0>;
343 interrupts = <0x2a 0x2>;
351 reg = <0x4600 0x100>;
352 clock-frequency = <0>;
353 interrupts = <0x1c 0x2>;
358 clock-frequency = <0>;
360 #address-cells = <0>;
362 reg = <0x40000 0x40000>;
369 reg = <0x41600 0x80>;
370 msi-available-ranges = <0 0x100>;
372 0xe0 0
373 0xe1 0
374 0xe2 0
375 0xe3 0
376 0xe4 0
377 0xe5 0
378 0xe6 0
379 0xe7 0>;
385 reg = <0xe0000 0x1000>;
396 reg = <0xfef08000 0x1000>;
397 bus-range = <0x0 0xff>;
398 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
399 0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
402 interrupts = <0x18 0x2>;
403 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
405 0x0000 0x0 0x0 0x1 &mpic 0x0 0x2
406 0x0000 0x0 0x0 0x2 &mpic 0x1 0x2
407 0x0000 0x0 0x0 0x3 &mpic 0x2 0x2
408 0x0000 0x0 0x0 0x4 &mpic 0x3 0x2
411 pcie@0 {
412 reg = <0 0 0 0 0>;
416 ranges = <0x02000000 0x0 0x80000000
417 0x02000000 0x0 0x80000000
418 0x0 0x40000000
420 0x01000000 0x0 0x00000000
421 0x01000000 0x0 0x00000000
422 0x0 0x00400000>;
432 reg = <0xfef09000 0x1000>;
433 bus-range = <0x0 0xff>;
434 ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
435 0x01000000 0x0 0x00000000 0xfe400000 0x0 0x00400000>;
438 interrupts = <0x19 0x2>;
439 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
441 0x0000 0x0 0x0 0x1 &mpic 0x4 0x2
442 0x0000 0x0 0x0 0x2 &mpic 0x5 0x2
443 0x0000 0x0 0x0 0x3 &mpic 0x6 0x2
444 0x0000 0x0 0x0 0x4 &mpic 0x7 0x2
447 pcie@0 {
448 reg = <0 0 0 0 0>;
452 ranges = <0x02000000 0x0 0xc0000000
453 0x02000000 0x0 0xc0000000
454 0x0 0x20000000
456 0x01000000 0x0 0x00000000
457 0x01000000 0x0 0x00000000
458 0x0 0x00400000>;