dts/fsl/p4080si-post.dtsi

14  *       names of its contributors may be used to endorse or promote products
36 	compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
38 	#address-cells = <2>;
39 	#size-cells = <1>;
44 	compatible = "fsl,p4080-pcie";
46 	#size-cells = <2>;
47 	#address-cells = <3>;
48 	bus-range = <0x0 0xff>;
49 	clock-frequency = <33333333>;
52 		reg = <0 0 0 0 0>;
53 		#interrupt-cells = <1>;
54 		#size-cells = <2>;
55 		#address-cells = <3>;
58 		interrupt-map-mask = <0xf800 0 0 7>;
59 		interrupt-map = <
71 	compatible = "fsl,p4080-pcie";
73 	#size-cells = <2>;
74 	#address-cells = <3>;
75 	bus-range = <0 0xff>;
76 	clock-frequency = <33333333>;
79 		reg = <0 0 0 0 0>;
80 		#interrupt-cells = <1>;
81 		#size-cells = <2>;
82 		#address-cells = <3>;
85 		interrupt-map-mask = <0xf800 0 0 7>;
86 		interrupt-map = <
98 	compatible = "fsl,p4080-pcie";
100 	#size-cells = <2>;
101 	#address-cells = <3>;
102 	bus-range = <0x0 0xff>;
103 	clock-frequency = <33333333>;
106 		reg = <0 0 0 0 0>;
107 		#interrupt-cells = <1>;
108 		#size-cells = <2>;
109 		#address-cells = <3>;
112 		interrupt-map-mask = <0xf800 0 0 7>;
113 		interrupt-map = <
126 	#address-cells = <2>;
127 	#size-cells = <2>;
128 	fsl,srio-rmu-handle = <&rmu>;
132 		#address-cells = <2>;
133 		#size-cells = <2>;
134 		cell-index = <1>;
138 		#address-cells = <2>;
139 		#size-cells = <2>;
140 		cell-index = <2>;
145 	#address-cells = <1>;
146 	#size-cells = <1>;
147 	compatible = "fsl,dcsr", "simple-bus";
149 	dcsr-epu@0 {
150 		compatible = "fsl,dcsr-epu";
154 		reg = <0x0 0x1000>;
156 	dcsr-npc {
157 		compatible = "fsl,dcsr-npc";
158 		reg = <0x1000 0x1000 0x1000000 0x8000>;
160 	dcsr-nxc@2000 {
161 		compatible = "fsl,dcsr-nxc";
162 		reg = <0x2000 0x1000>;
164 	dcsr-corenet {
165 		compatible = "fsl,dcsr-corenet";
166 		reg = <0x8000 0x1000 0xB0000 0x1000>;
168 	dcsr-dpaa@9000 {
169 		compatible = "fsl,p4080-dcsr-dpaa", "fsl,dcsr-dpaa";
170 		reg = <0x9000 0x1000>;
172 	dcsr-ocn@11000 {
173 		compatible = "fsl,p4080-dcsr-ocn", "fsl,dcsr-ocn";
174 		reg = <0x11000 0x1000>;
176 	dcsr-ddr@12000 {
177 		compatible = "fsl,dcsr-ddr";
178 		dev-handle = <&ddr1>;
179 		reg = <0x12000 0x1000>;
181 	dcsr-ddr@13000 {
182 		compatible = "fsl,dcsr-ddr";
183 		dev-handle = <&ddr2>;
184 		reg = <0x13000 0x1000>;
186 	dcsr-nal@18000 {
187 		compatible = "fsl,p4080-dcsr-nal", "fsl,dcsr-nal";
188 		reg = <0x18000 0x1000>;
190 	dcsr-rcpm@22000 {
191 		compatible = "fsl,p4080-dcsr-rcpm", "fsl,dcsr-rcpm";
192 		reg = <0x22000 0x1000>;
194 	dcsr-cpu-sb-proxy@40000 {
195 		compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
196 		cpu-handle = <&cpu0>;
197 		reg = <0x40000 0x1000>;
199 	dcsr-cpu-sb-proxy@41000 {
200 		compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
201 		cpu-handle = <&cpu1>;
202 		reg = <0x41000 0x1000>;
204 	dcsr-cpu-sb-proxy@42000 {
205 		compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
206 		cpu-handle = <&cpu2>;
207 		reg = <0x42000 0x1000>;
209 	dcsr-cpu-sb-proxy@43000 {
210 		compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
211 		cpu-handle = <&cpu3>;
212 		reg = <0x43000 0x1000>;
214 	dcsr-cpu-sb-proxy@44000 {
215 		compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
216 		cpu-handle = <&cpu4>;
217 		reg = <0x44000 0x1000>;
219 	dcsr-cpu-sb-proxy@45000 {
220 		compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
221 		cpu-handle = <&cpu5>;
222 		reg = <0x45000 0x1000>;
224 	dcsr-cpu-sb-proxy@46000 {
225 		compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
226 		cpu-handle = <&cpu6>;
227 		reg = <0x46000 0x1000>;
229 	dcsr-cpu-sb-proxy@47000 {
230 		compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
231 		cpu-handle = <&cpu7>;
232 		reg = <0x47000 0x1000>;
238 	#address-cells = <1>;
239 	#size-cells = <1>;
241 	compatible = "simple-bus";
243 	soc-sram-error {
244 		compatible = "fsl,soc-sram-error";
248 	corenet-law@0 {
249 		compatible = "fsl,corenet-law";
250 		reg = <0x0 0x1000>;
251 		fsl,num-laws = <32>;
254 	ddr1: memory-controller@8000 {
255 		compatible = "fsl,qoriq-memory-controller-v4.4", "fsl,qoriq-memory-controller";
256 		reg = <0x8000 0x1000>;
260 	ddr2: memory-controller@9000 {
261 		compatible = "fsl,qoriq-memory-controller-v4.4","fsl,qoriq-memory-controller";
262 		reg = <0x9000 0x1000>;
266 	cpc: l3-cache-controller@10000 {
267 		compatible = "fsl,p4080-l3-cache-controller", "cache";
268 		reg = <0x10000 0x1000
274 	corenet-cf@18000 {
275 		compatible = "fsl,corenet-cf";
276 		reg = <0x18000 0x1000>;
278 		fsl,ccf-num-csdids = <32>;
279 		fsl,ccf-num-snoopids = <32>;
283 		compatible = "fsl,pamu-v1.0", "fsl,pamu";
284 		reg = <0x20000 0x5000>;
290 /include/ "qoriq-rmu-0.dtsi"
291 /include/ "qoriq-mpic.dtsi"
293 	guts: global-utilities@e0000 {
294 		compatible = "fsl,qoriq-device-config-1.0";
295 		reg = <0xe0000 0xe00>;
296 		fsl,has-rstcr;
297 		#sleep-cells = <1>;
298 		fsl,liodn-bits = <12>;
301 	pins: global-utilities@e0e00 {
302 		compatible = "fsl,qoriq-pin-control-1.0";
303 		reg = <0xe0e00 0x200>;
304 		#sleep-cells = <2>;
307 	clockgen: global-utilities@e1000 {
308 		compatible = "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0";
309 		reg = <0xe1000 0x1000>;
310 		clock-frequency = <0>;
313 	rcpm: global-utilities@e2000 {
314 		compatible = "fsl,qoriq-rcpm-1.0";
315 		reg = <0xe2000 0x1000>;
316 		#sleep-cells = <1>;
320 		compatible = "fsl,p4080-sfp", "fsl,qoriq-sfp-1.0";
321 		reg	   = <0xe8000 0x1000>;
325 		compatible = "fsl,p4080-serdes";
326 		reg	   = <0xea000 0x1000>;
329 /include/ "qoriq-dma-0.dtsi"
330 /include/ "qoriq-dma-1.dtsi"
331 /include/ "qoriq-espi-0.dtsi"
333 		fsl,espi-num-chipselects = <4>;
336 /include/ "qoriq-esdhc-0.dtsi"
338 		voltage-ranges = <3300 3300>;
339 		sdhci,auto-cmd12;
342 /include/ "qoriq-i2c-0.dtsi"
343 /include/ "qoriq-i2c-1.dtsi"
344 /include/ "qoriq-duart-0.dtsi"
345 /include/ "qoriq-duart-1.dtsi"
346 /include/ "qoriq-gpio-0.dtsi"
347 /include/ "qoriq-usb2-mph-0.dtsi"
348 /include/ "qoriq-usb2-dr-0.dtsi"
349 /include/ "qoriq-sec4.0-0.dtsi"