Lines Matching +full:interrupt +full:- +full:map
4 * Copyright 2008-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
28 #address-cells = <1>;
29 #size-cells = <0>;
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
37 i-cache-line-size = <32>;
38 d-cache-line-size = <32>;
39 i-cache-size = <32768>;
40 d-cache-size = <32768>;
41 dcr-controller;
42 dcr-access-method = "native";
43 next-level-cache = <&L2C0>;
49 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
52 UIC0: interrupt-controller0 {
53 compatible = "ibm,uic-460ex","ibm,uic";
54 interrupt-controller;
55 cell-index = <0>;
56 dcr-reg = <0x0c0 0x009>;
57 #address-cells = <0>;
58 #size-cells = <0>;
59 #interrupt-cells = <2>;
62 UIC1: interrupt-controller1 {
63 compatible = "ibm,uic-460ex","ibm,uic";
64 interrupt-controller;
65 cell-index = <1>;
66 dcr-reg = <0x0d0 0x009>;
67 #address-cells = <0>;
68 #size-cells = <0>;
69 #interrupt-cells = <2>;
71 interrupt-parent = <&UIC0>;
74 UIC2: interrupt-controller2 {
75 compatible = "ibm,uic-460ex","ibm,uic";
76 interrupt-controller;
77 cell-index = <2>;
78 dcr-reg = <0x0e0 0x009>;
79 #address-cells = <0>;
80 #size-cells = <0>;
81 #interrupt-cells = <2>;
83 interrupt-parent = <&UIC0>;
86 UIC3: interrupt-controller3 {
87 compatible = "ibm,uic-460ex","ibm,uic";
88 interrupt-controller;
89 cell-index = <3>;
90 dcr-reg = <0x0f0 0x009>;
91 #address-cells = <0>;
92 #size-cells = <0>;
93 #interrupt-cells = <2>;
95 interrupt-parent = <&UIC0>;
99 compatible = "ibm,sdr-460ex";
100 dcr-reg = <0x00e 0x002>;
104 compatible = "ibm,cpr-460ex";
105 dcr-reg = <0x00c 0x002>;
110 dcr-access-method = "native";
111 dcr-reg = <0x160 0x003>;
112 unused-units = <0x00000100>;
113 idle-doze = <0x02000000>;
118 compatible = "ibm,l2-cache-460ex", "ibm,l2-cache";
119 dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */
121 cache-line-size = <32>; /* 32 bytes */
122 cache-size = <262144>; /* L2, 256K */
123 interrupt-parent = <&UIC1>;
128 compatible = "ibm,plb-460ex", "ibm,plb4";
129 #address-cells = <2>;
130 #size-cells = <1>;
132 clock-frequency = <0>; /* Filled in by U-Boot */
135 compatible = "ibm,sdram-460ex", "ibm,sdram-405gp";
136 dcr-reg = <0x010 0x002>;
140 compatible = "amcc,ppc460ex-crypto", "amcc,ppc4xx-crypto";
142 interrupt-parent = <&UIC0>;
147 compatible = "amcc,ppc460ex-rng", "ppc4xx-rng";
152 compatible = "ibm,mcmal-460ex", "ibm,mcmal2";
153 dcr-reg = <0x180 0x062>;
154 num-tx-chans = <2>;
155 num-rx-chans = <16>;
156 #address-cells = <0>;
157 #size-cells = <0>;
158 interrupt-parent = <&UIC2>;
167 compatible = "ibm,usb-ehci-460ex", "usb-ehci";
168 interrupt-parent = <&UIC2>;
174 compatible = "ohci-le";
176 interrupt-parent = <&UIC2>;
181 compatible = "amcc,dwc-otg";
183 interrupt-parent = <&USBOTG0>;
184 #interrupt-cells = <1>;
185 #address-cells = <0>;
186 #size-cells = <0>;
188 interrupt-map = </* USB-OTG */ 0x0 &UIC2 0x1c 0x4
189 /* HIGH-POWER */ 0x1 &UIC1 0x1a 0x8
194 compatible = "amcc,sata-460ex";
196 interrupt-parent = <&UIC3>;
202 compatible = "ibm,opb-460ex", "ibm,opb";
203 #address-cells = <1>;
204 #size-cells = <1>;
206 clock-frequency = <0>; /* Filled in by U-Boot */
209 compatible = "ibm,ebc-460ex", "ibm,ebc";
210 dcr-reg = <0x012 0x002>;
211 #address-cells = <2>;
212 #size-cells = <1>;
213 clock-frequency = <0>; /* Filled in by U-Boot */
214 /* ranges property is supplied by U-Boot */
216 interrupt-parent = <&UIC1>;
219 compatible = "amd,s29gl512n", "cfi-flash";
220 bank-width = <2>;
222 #address-cells = <1>;
223 #size-cells = <1>;
249 label = "u-boot";
255 compatible = "amcc,ppc460ex-bcsr";
263 bank-settings = <0x80002222>;
264 #address-cells = <1>;
265 #size-cells = <1>;
268 #address-cells = <1>;
269 #size-cells = <1>;
272 label = "u-boot";
287 virtual-reg = <0xef600300>;
288 clock-frequency = <0>; /* Filled in by U-Boot */
289 current-speed = <0>; /* Filled in by U-Boot */
290 interrupt-parent = <&UIC1>;
298 virtual-reg = <0xef600400>;
299 clock-frequency = <0>; /* Filled in by U-Boot */
300 current-speed = <0>; /* Filled in by U-Boot */
301 interrupt-parent = <&UIC0>;
306 compatible = "ibm,iic-460ex", "ibm,iic";
308 interrupt-parent = <&UIC0>;
310 #address-cells = <1>;
311 #size-cells = <0>;
315 interrupt-parent = <&UIC2>;
321 interrupt-parent = <&UIC1>;
327 compatible = "ibm,iic-460ex", "ibm,iic";
329 interrupt-parent = <&UIC0>;
334 compatible = "ibm,ppc4xx-gpio";
336 gpio-controller;
339 ZMII0: emac-zmii@ef600d00 {
340 compatible = "ibm,zmii-460ex", "ibm,zmii";
344 RGMII0: emac-rgmii@ef601500 {
345 compatible = "ibm,rgmii-460ex", "ibm,rgmii";
347 has-mdio;
350 TAH0: emac-tah@ef601350 {
351 compatible = "ibm,tah-460ex", "ibm,tah";
355 TAH1: emac-tah@ef601450 {
356 compatible = "ibm,tah-460ex", "ibm,tah";
362 compatible = "ibm,emac-460ex", "ibm,emac4sync";
363 interrupt-parent = <&EMAC0>;
365 #interrupt-cells = <1>;
366 #address-cells = <0>;
367 #size-cells = <0>;
368 interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
371 local-mac-address = [000000000000]; /* Filled in by U-Boot */
372 mal-device = <&MAL0>;
373 mal-tx-channel = <0>;
374 mal-rx-channel = <0>;
375 cell-index = <0>;
376 max-frame-size = <9000>;
377 rx-fifo-size = <4096>;
378 tx-fifo-size = <2048>;
379 rx-fifo-size-gige = <16384>;
380 phy-mode = "rgmii";
381 phy-map = <0x00000000>;
382 rgmii-device = <&RGMII0>;
383 rgmii-channel = <0>;
384 tah-device = <&TAH0>;
385 tah-channel = <0>;
386 has-inverted-stacr-oc;
387 has-new-stacr-staopc;
392 compatible = "ibm,emac-460ex", "ibm,emac4sync";
393 interrupt-parent = <&EMAC1>;
395 #interrupt-cells = <1>;
396 #address-cells = <0>;
397 #size-cells = <0>;
398 interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4
401 local-mac-address = [000000000000]; /* Filled in by U-Boot */
402 mal-device = <&MAL0>;
403 mal-tx-channel = <1>;
404 mal-rx-channel = <8>;
405 cell-index = <1>;
406 max-frame-size = <9000>;
407 rx-fifo-size = <4096>;
408 tx-fifo-size = <2048>;
409 rx-fifo-size-gige = <16384>;
410 phy-mode = "rgmii";
411 phy-map = <0x00000000>;
412 rgmii-device = <&RGMII0>;
413 rgmii-channel = <1>;
414 tah-device = <&TAH1>;
415 tah-channel = <1>;
416 has-inverted-stacr-oc;
417 has-new-stacr-staopc;
418 mdio-device = <&EMAC0>;
424 #interrupt-cells = <1>;
425 #size-cells = <2>;
426 #address-cells = <3>;
427 compatible = "ibm,plb-pcix-460ex", "ibm,plb-pcix";
429 large-inbound-windows;
430 enable-msi-hole;
445 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
448 bus-range = <0x0 0x3f>;
450 /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
451 interrupt-map-mask = <0x0 0x0 0x0 0x0>;
452 interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >;
457 #interrupt-cells = <1>;
458 #size-cells = <2>;
459 #address-cells = <3>;
460 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
465 dcr-reg = <0x100 0x020>;
466 sdr-base = <0x300>;
476 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
479 bus-range = <0x40 0x7f>;
483 * We are de-swizzling here because the numbers are actually for
486 * below are basically de-swizzled numbers.
489 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
490 interrupt-map = <
499 #interrupt-cells = <1>;
500 #size-cells = <2>;
501 #address-cells = <3>;
502 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
507 dcr-reg = <0x120 0x020>;
508 sdr-base = <0x340>;
518 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
521 bus-range = <0x80 0xbf>;
525 * We are de-swizzling here because the numbers are actually for
528 * below are basically de-swizzled numbers.
531 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
532 interrupt-map = <
539 MSI: ppc4xx-msi@C10000000 {
540 compatible = "amcc,ppc4xx-msi", "ppc4xx-msi";
542 sdr-base = <0x36C>;
543 msi-data = <0x00000000>;
544 msi-mask = <0x44440000>;
545 interrupt-count = <3>;
547 interrupt-parent = <&UIC3>;
548 #interrupt-cells = <1>;
549 #address-cells = <0>;
550 #size-cells = <0>;
551 interrupt-map = <0 &UIC3 0x18 1