include/asm/serial-regs.h

1 /* MN10300 on-board serial port module registers
15 #include <asm/cpu-regs.h>
16 #include <asm/intctl-regs.h>
22 #define	SC01CTR_CK		0x0007	/* clock source select */
23 #define	SC01CTR_CK_IOCLK_8	0x0001	/* - 1/8 IOCLK */
24 #define	SC01CTR_CK_IOCLK_32	0x0002	/* - 1/32 IOCLK */
25 #define	SC01CTR_CK_EXTERN_8	0x0006	/* - 1/8 external closk */
26 #define	SC01CTR_CK_EXTERN	0x0007	/* - external closk */
28 #define	SC0CTR_CK_TM8UFLOW_8	0x0000	/* - 1/8 timer 8 underflow (serial port 0 only) */
29 #define	SC0CTR_CK_TM2UFLOW_2	0x0003	/* - 1/2 timer 2 underflow (serial port 0 only) */
30 #define	SC0CTR_CK_TM0UFLOW_8	0x0004	/* - 1/8 timer 0 underflow (serial port 0 only) */
31 #define	SC0CTR_CK_TM2UFLOW_8	0x0005	/* - 1/8 timer 2 underflow (serial port 0 only) */
32 #define	SC1CTR_CK_TM9UFLOW_8	0x0000	/* - 1/8 timer 9 underflow (serial port 1 only) */
33 #define	SC1CTR_CK_TM3UFLOW_2	0x0003	/* - 1/2 timer 3 underflow (serial port 1 only) */
34 #define	SC1CTR_CK_TM1UFLOW_8	0x0004	/* - 1/8 timer 1 underflow (serial port 1 only) */
35 #define	SC1CTR_CK_TM3UFLOW_8	0x0005	/* - 1/8 timer 3 underflow (serial port 1 only) */
37 #define	SC0CTR_CK_TM8UFLOW_8	0x0000	/* - 1/8 timer 8 underflow (serial port 0 only) */
38 #define	SC0CTR_CK_TM0UFLOW_8	0x0004	/* - 1/8 timer 0 underflow (serial port 0 only) */
39 #define	SC0CTR_CK_TM2UFLOW_8	0x0005	/* - 1/8 timer 2 underflow (serial port 0 only) */
40 #define	SC1CTR_CK_TM12UFLOW_8	0x0000	/* - 1/8 timer 12 underflow (serial port 1 only) */
43 #define	SC01CTR_STB_1BIT	0x0000	/* - 1 stop bit */
44 #define	SC01CTR_STB_2BIT	0x0008	/* - 2 stop bits */
46 #define	SC01CTR_PB_NONE		0x0000	/* - no parity */
47 #define	SC01CTR_PB_FIXED0	0x0040	/* - fixed at 0 */
48 #define	SC01CTR_PB_FIXED1	0x0050	/* - fixed at 1 */
49 #define	SC01CTR_PB_EVEN		0x0060	/* - even parity */
50 #define	SC01CTR_PB_ODD		0x0070	/* - odd parity */
52 #define	SC01CTR_CLN_7BIT	0x0000	/* - 7 bit chars */
53 #define	SC01CTR_CLN_8BIT	0x0080	/* - 8 bit chars */
56 #define	SC01CTR_OD_LSBFIRST	0x0000	/* - LSB first */
57 #define	SC01CTR_OD_MSBFIRST	0x0200	/* - MSB first */
59 #define SC01CTR_MD_STST_SYNC	0x0000	/* - start-stop synchronous */
60 #define SC01CTR_MD_CLOCK_SYNC1	0x0400	/* - clock synchronous 1 */
61 #define SC01CTR_MD_I2C		0x0800	/* - I2C mode */
62 #define SC01CTR_MD_CLOCK_SYNC2	0x0c00	/* - clock synchronous 2 */
111 #define	SC2CTR_CK		0x0003	/* clock source select */
112 #define	SC2CTR_CK_TM10UFLOW	0x0000	/* - timer 10 underflow */
113 #define	SC2CTR_CK_TM2UFLOW	0x0001	/* - timer 2 underflow */
114 #define	SC2CTR_CK_EXTERN	0x0002	/* - external closk */
115 #define	SC2CTR_CK_TM3UFLOW	0x0003	/* - timer 3 underflow */
117 #define	SC2CTR_CK		0x0007	/* clock source select */
118 #define	SC2CTR_CK_TM9UFLOW_8	0x0000	/* - 1/8 timer 9 underflow */
119 #define	SC2CTR_CK_IOCLK_8	0x0001	/* - 1/8 IOCLK */
120 #define	SC2CTR_CK_IOCLK_32	0x0002	/* - 1/32 IOCLK */
121 #define	SC2CTR_CK_TM3UFLOW_2	0x0003	/* - 1/2 timer 3 underflow */
122 #define	SC2CTR_CK_TM1UFLOW_8	0x0004	/* - 1/8 timer 1 underflow */
123 #define	SC2CTR_CK_TM3UFLOW_8	0x0005	/* - 1/8 timer 3 underflow */
124 #define	SC2CTR_CK_EXTERN_8	0x0006	/* - 1/8 external closk */
125 #define	SC2CTR_CK_EXTERN	0x0007	/* - external closk */
128 #define	SC2CTR_STB_1BIT		0x0000	/* - 1 stop bit */
129 #define	SC2CTR_STB_2BIT		0x0008	/* - 2 stop bits */
131 #define	SC2CTR_PB_NONE		0x0000	/* - no parity */
132 #define	SC2CTR_PB_FIXED0	0x0040	/* - fixed at 0 */
133 #define	SC2CTR_PB_FIXED1	0x0050	/* - fixed at 1 */
134 #define	SC2CTR_PB_EVEN		0x0060	/* - even parity */
135 #define	SC2CTR_PB_ODD		0x0070	/* - odd parity */
137 #define	SC2CTR_CLN_7BIT		0x0000	/* - 7 bit chars */
138 #define	SC2CTR_CLN_8BIT		0x0080	/* - 8 bit chars */
141 #define	SC2CTR_OD_LSBFIRST	0x0000	/* - LSB first */
142 #define	SC2CTR_OD_MSBFIRST	0x0200	/* - MSB first */
144 #define	SC2CTR_TWS_XCTS_HIGH	0x0000	/* - interrupt TX when XCTS high */
145 #define	SC2CTR_TWS_XCTS_LOW	0x1000	/* - interrupt TX when XCTS low */