include/asm/m5307sim.h

4  *	m5307sim.h -- ColdFire 5307 System Integration Module support.
18 #define	CPU_INSTR_PER_JIFFY	3
40 #define	MCFSIM_ICR3		0x4f		/* Intr Ctrl reg 3 (r/w) */
50 #define MCFSIM_CSAR0		0x80		/* CS 0 Address 0 reg (r/w) */
51 #define MCFSIM_CSMR0		0x84		/* CS 0 Mask 0 reg (r/w) */
52 #define MCFSIM_CSCR0		0x8a		/* CS 0 Control reg (r/w) */
53 #define MCFSIM_CSAR1		0x8c		/* CS 1 Address reg (r/w) */
54 #define MCFSIM_CSMR1		0x90		/* CS 1 Mask reg (r/w) */
55 #define MCFSIM_CSCR1		0x96		/* CS 1 Control reg (r/w) */
58 #define MCFSIM_CSBAR		0x98		/* CS Base Address reg (r/w) */
59 #define MCFSIM_CSBAMR		0x9c		/* CS Base Mask reg (r/w) */
60 #define MCFSIM_CSMR2		0x9e		/* CS 2 Mask reg (r/w) */
61 #define MCFSIM_CSCR2		0xa2		/* CS 2 Control reg (r/w) */
62 #define MCFSIM_CSMR3		0xaa		/* CS 3 Mask reg (r/w) */
63 #define MCFSIM_CSCR3		0xae		/* CS 3 Control reg (r/w) */
64 #define MCFSIM_CSMR4		0xb6		/* CS 4 Mask reg (r/w) */
65 #define MCFSIM_CSCR4		0xba		/* CS 4 Control reg (r/w) */
66 #define MCFSIM_CSMR5		0xc2		/* CS 5 Mask reg (r/w) */
67 #define MCFSIM_CSCR5		0xc6		/* CS 5 Control reg (r/w) */
68 #define MCFSIM_CSMR6		0xce		/* CS 6 Mask reg (r/w) */
69 #define MCFSIM_CSCR6		0xd2		/* CS 6 Control reg (r/w) */
70 #define MCFSIM_CSMR7		0xda		/* CS 7 Mask reg (r/w) */
71 #define MCFSIM_CSCR7		0xde		/* CS 7 Control reg (r/w) */
73 #define MCFSIM_CSAR2		0x98		/* CS 2 Address reg (r/w) */
74 #define MCFSIM_CSMR2		0x9c		/* CS 2 Mask reg (r/w) */
75 #define MCFSIM_CSCR2		0xa2		/* CS 2 Control reg (r/w) */
76 #define MCFSIM_CSAR3		0xa4		/* CS 3 Address reg (r/w) */
77 #define MCFSIM_CSMR3		0xa8		/* CS 3 Mask reg (r/w) */
78 #define MCFSIM_CSCR3		0xae		/* CS 3 Control reg (r/w) */
79 #define MCFSIM_CSAR4		0xb0		/* CS 4 Address reg (r/w) */
80 #define MCFSIM_CSMR4		0xb4		/* CS 4 Mask reg (r/w) */
81 #define MCFSIM_CSCR4		0xba		/* CS 4 Control reg (r/w) */
82 #define MCFSIM_CSAR5		0xbc		/* CS 5 Address reg (r/w) */
83 #define MCFSIM_CSMR5		0xc0		/* CS 5 Mask reg (r/w) */
84 #define MCFSIM_CSCR5		0xc6		/* CS 5 Control reg (r/w) */
85 #define MCFSIM_CSAR6		0xc8		/* CS 6 Address reg (r/w) */
86 #define MCFSIM_CSMR6		0xcc		/* CS 6 Mask reg (r/w) */
87 #define MCFSIM_CSCR6		0xd2		/* CS 6 Control reg (r/w) */
88 #define MCFSIM_CSAR7		0xd4		/* CS 7 Address reg (r/w) */
89 #define MCFSIM_CSMR7		0xd8		/* CS 7 Mask reg (r/w) */
90 #define MCFSIM_CSCR7		0xde		/* CS 7 Control reg (r/w) */
114 #define MCFDMA_BASE3		(MCF_MBAR + 0x3C0)	/* Base address DMA 3 */
131 #define MCFGPIO_IRQ_MAX			-1
132 #define MCFGPIO_IRQ_VECBASE		-1
135 /* Definition offset address for CS2-7  -- old mask 5307 */
156 #define	MCFSIM_DMA3ICR		MCFSIM_ICR9	/* DMA 3 ICR */