Lines Matching +full:interrupt +full:- +full:map
6 * Copyright (C) 2003-2006 Silicon Graphics, Inc. All Rights Reserved.
10 #include <linux/interrupt.h>
48 * TIOCE Coretalk Address Range 0x0 - 0x07ff_ffff. This includes the
50 * spaces from table 2-1 of the "CE Programmer's Reference Overview" document.
61 if (kern->ce_common->ce_rev != TIOCE_REV_A) in tioce_mmr_war_pre()
64 mmr_base = kern->ce_common->ce_pcibus.bs_base; in tioce_mmr_war_pre()
65 mmr_offset = (unsigned long)mmr_addr - mmr_base; in tioce_mmr_war_pre()
87 if (kern->ce_common->ce_rev != TIOCE_REV_A) in tioce_mmr_war_post()
90 mmr_base = kern->ce_common->ce_pcibus.bs_base; in tioce_mmr_war_post()
91 mmr_offset = (unsigned long)mmr_addr - mmr_base; in tioce_mmr_war_post()
166 #define ATE_PAGEMASK(ps) ((ps)-1)
170 (ATE_PAGE((start)+(len)-1, pagesize) - ATE_PAGE(start, pagesize) + 1)
177 * Flavors of ate-based mapping supported by tioce_alloc_map()
189 * tioce_dma_d64 - create a DMA mapping using 64-bit direct mode
192 * Map @ct_addr into 64-bit CE bus space. No device context is necessary
198 * 63 - must be 1 to indicate d64 mode to CE hardware
199 * 62 - barrier bit ... controlled with tioce_dma_barrier()
200 * 61 - msi bit ... specified through dma_flags
201 * 60:54 - reserved, MBZ
216 * pcidev_to_tioce - return misc ce related pointers given a pci_dev
222 * Return pointers to various CE-related structures for the CE upstream of
234 ce_common = (struct tioce_common *)pcidev_info->pdi_pcibus_info; in pcidev_to_tioce()
235 ce_kernel = (struct tioce_kernel *)ce_common->ce_kernel_private; in pcidev_to_tioce()
238 *base = (struct tioce __iomem *)ce_common->ce_pcibus.bs_base; in pcidev_to_tioce()
243 * we use port as a zero-based value internally, even though the in pcidev_to_tioce()
244 * documentation is 1-based. in pcidev_to_tioce()
248 (pdev->bus->number < ce_kernel->ce_port1_secondary) ? 0 : 1; in pcidev_to_tioce()
252 * tioce_alloc_map - Given a coretalk address, map it to pcie bus address
253 * space using one of the various ATE-based address modes.
255 * @type: map mode to use
256 * @port: 0-based port that the requesting device is downstream of
257 * @ct_addr: the coretalk address to map
258 * @len: number of bytes to map
282 struct tioce_dmamap *map; in tioce_alloc_map() local
284 ce_mmr = (struct tioce __iomem *)ce_kern->ce_common->ce_pcibus.bs_base; in tioce_alloc_map()
290 * super-page (TIOCE_ATE_M40S) mode. in tioce_alloc_map()
293 entries = TIOCE_NUM_M3240_ATES - 64; in tioce_alloc_map()
294 ate_shadow = ce_kern->ce_ate3240_shadow; in tioce_alloc_map()
295 ate_reg = ce_mmr->ce_ure_ate3240; in tioce_alloc_map()
296 pagesize = ce_kern->ce_ate3240_pagesize; in tioce_alloc_map()
303 ate_shadow = ce_kern->ce_ate40_shadow; in tioce_alloc_map()
304 ate_reg = ce_mmr->ce_ure_ate40; in tioce_alloc_map()
311 * ate3240 entries 0-31 are dedicated to port1 super-page in tioce_alloc_map()
312 * mappings. ate3240 entries 32-63 are dedicated to port2. in tioce_alloc_map()
316 ate_shadow = ce_kern->ce_ate3240_shadow; in tioce_alloc_map()
317 ate_reg = ce_mmr->ce_ure_ate3240; in tioce_alloc_map()
334 last = first + entries - nates; in tioce_alloc_map()
350 map = kzalloc(sizeof(struct tioce_dmamap), GFP_ATOMIC); in tioce_alloc_map()
351 if (!map) in tioce_alloc_map()
364 map->refcnt = 1; in tioce_alloc_map()
365 map->nbytes = nates * pagesize; in tioce_alloc_map()
366 map->ct_start = ct_addr & ~ATE_PAGEMASK(pagesize); in tioce_alloc_map()
367 map->pci_start = bus_base + (i * pagesize); in tioce_alloc_map()
368 map->ate_hw = &ate_reg[i]; in tioce_alloc_map()
369 map->ate_shadow = &ate_shadow[i]; in tioce_alloc_map()
370 map->ate_count = nates; in tioce_alloc_map()
372 list_add(&map->ce_dmamap_list, &ce_kern->ce_dmamap_list); in tioce_alloc_map()
374 return (map->pci_start + (ct_addr - map->ct_start)); in tioce_alloc_map()
378 * tioce_dma_d32 - create a DMA mapping using 32-bit direct mode
382 * Map @paddr into 32-bit bus space of the CE associated with @pcidev_info.
403 if (ce_kern->ce_port[port].dirmap_refcnt == 0) { in tioce_dma_d32()
406 ce_kern->ce_port[port].dirmap_shadow = ct_upper; in tioce_dma_d32()
407 tioce_mmr_storei(ce_kern, &ce_mmr->ce_ure_dir_map[port], in tioce_dma_d32()
409 tmp = ce_mmr->ce_ure_dir_map[port]; in tioce_dma_d32()
412 dma_ok = (ce_kern->ce_port[port].dirmap_shadow == ct_upper); in tioce_dma_d32()
415 ce_kern->ce_port[port].dirmap_refcnt++; in tioce_dma_d32()
424 * tioce_dma_barrier - swizzle a TIOCE bus address to include or exclude
449 * tioce_dma_unmap - release CE mapping resources
475 spin_lock_irqsave(&ce_kern->ce_lock, flags); in tioce_dma_unmap()
478 if (--ce_kern->ce_port[port].dirmap_refcnt == 0) { in tioce_dma_unmap()
479 ce_kern->ce_port[port].dirmap_shadow = 0; in tioce_dma_unmap()
480 tioce_mmr_storei(ce_kern, &ce_mmr->ce_ure_dir_map[port], in tioce_dma_unmap()
484 struct tioce_dmamap *map; in tioce_dma_unmap() local
486 list_for_each_entry(map, &ce_kern->ce_dmamap_list, in tioce_dma_unmap()
490 last = map->pci_start + map->nbytes - 1; in tioce_dma_unmap()
491 if (bus_addr >= map->pci_start && bus_addr <= last) in tioce_dma_unmap()
495 if (&map->ce_dmamap_list == &ce_kern->ce_dmamap_list) { in tioce_dma_unmap()
497 "%s: %s - no map found for bus_addr 0x%llx\n", in tioce_dma_unmap()
499 } else if (--map->refcnt == 0) { in tioce_dma_unmap()
500 for (i = 0; i < map->ate_count; i++) { in tioce_dma_unmap()
501 map->ate_shadow[i] = 0; in tioce_dma_unmap()
502 tioce_mmr_storei(ce_kern, &map->ate_hw[i], 0); in tioce_dma_unmap()
505 list_del(&map->ce_dmamap_list); in tioce_dma_unmap()
506 kfree(map); in tioce_dma_unmap()
510 spin_unlock_irqrestore(&ce_kern->ce_lock, flags); in tioce_dma_unmap()
514 * tioce_do_dma_map - map pages for PCI DMA
516 * @paddr: host physical address to map
517 * @byte_count: bytes to map
530 struct tioce_dmamap *map; in tioce_do_dma_map() local
534 dma_mask = (barrier) ? pdev->dev.coherent_dma_mask : pdev->dma_mask; in tioce_do_dma_map()
546 * If the device can generate 64 bit addresses, create a D64 map. in tioce_do_dma_map()
556 spin_lock_irqsave(&ce_kern->ce_lock, flags); in tioce_do_dma_map()
559 * D64 didn't work ... See if we have an existing map that covers in tioce_do_dma_map()
561 * an existing map might have been done in a mode using more pci in tioce_do_dma_map()
564 list_for_each_entry(map, &ce_kern->ce_dmamap_list, ce_dmamap_list) { in tioce_do_dma_map()
567 last = map->ct_start + map->nbytes - 1; in tioce_do_dma_map()
568 if (ct_addr >= map->ct_start && in tioce_do_dma_map()
569 ct_addr + byte_count - 1 <= last && in tioce_do_dma_map()
570 map->pci_start <= dma_mask) { in tioce_do_dma_map()
571 map->refcnt++; in tioce_do_dma_map()
572 mapaddr = map->pci_start + (ct_addr - map->ct_start); in tioce_do_dma_map()
578 * If we don't have a map yet, and the card can generate 40 in tioce_do_dma_map()
580 * support a barrier bit, so if we need a consistent map these in tioce_do_dma_map()
585 * We have two options for 40-bit mappings: 16GB "super" ATEs in tioce_do_dma_map()
598 tioce_alloc_map(ce_kern, TIOCE_ATE_M40, -1, in tioce_do_dma_map()
602 mapaddr = tioce_alloc_map(ce_kern, TIOCE_ATE_M40, -1, in tioce_do_dma_map()
614 * 32-bit direct is the next mode to try in tioce_do_dma_map()
620 * Last resort, try 32-bit ATE-based map. in tioce_do_dma_map()
624 tioce_alloc_map(ce_kern, TIOCE_ATE_M32, -1, ct_addr, in tioce_do_dma_map()
627 spin_unlock_irqrestore(&ce_kern->ce_lock, flags); in tioce_do_dma_map()
637 * tioce_dma - standard pci dma map interface
638 * @pdev: pci device requesting the map
639 * @paddr: system physical address to map into pci space
640 * @byte_count: # bytes to map
642 * Simply call tioce_do_dma_map() to create a map with the barrier bit clear
652 * tioce_dma_consistent - consistent pci dma map interface
653 * @pdev: pci device requesting the map
654 * @paddr: system physical address to map into pci space
655 * @byte_count: # bytes to map
657 * Simply call tioce_do_dma_map() to create a map with the barrier bit set
667 * tioce_error_intr_handler - SGI TIO CE error interrupt handler
671 * Handle a CE error interrupt. Simply a wrapper around a SAL call which
683 soft->ce_pcibus.bs_persist_segment, in tioce_error_intr_handler()
684 soft->ce_pcibus.bs_persist_busnum, 0, 0, 0, 0, 0); in tioce_error_intr_handler()
693 * tioce_reserve_m32 - reserve M32 ATEs for the indicated address range
707 ce_mmr = (struct tioce __iomem *)ce_kern->ce_common->ce_pcibus.bs_base; in tioce_reserve_m32()
708 ps = ce_kern->ce_ate3240_pagesize; in tioce_reserve_m32()
710 last_ate = ate_index + ATE_NPAGES(base, limit-base+1, ps) - 1; in tioce_reserve_m32()
716 last_ate = TIOCE_NUM_M3240_ATES - 1; in tioce_reserve_m32()
722 ce_kern->ce_ate3240_shadow[ate_index] = ate; in tioce_reserve_m32()
723 tioce_mmr_storei(ce_kern, &ce_mmr->ce_ure_ate3240[ate_index], in tioce_reserve_m32()
730 * tioce_kern_init - init kernel structures related to a given TIOCE
749 tioce_kern->ce_common = tioce_common; in tioce_kern_init()
750 spin_lock_init(&tioce_kern->ce_lock); in tioce_kern_init()
751 INIT_LIST_HEAD(&tioce_kern->ce_dmamap_list); in tioce_kern_init()
752 tioce_common->ce_kernel_private = (u64) tioce_kern; in tioce_kern_init()
761 seg = tioce_common->ce_pcibus.bs_persist_segment; in tioce_kern_init()
762 bus = tioce_common->ce_pcibus.bs_persist_busnum; in tioce_kern_init()
765 tioce_kern->ce_port1_secondary = (u8) tmp; in tioce_kern_init()
772 tioce_mmr = (struct tioce __iomem *)tioce_common->ce_pcibus.bs_base; in tioce_kern_init()
773 tioce_mmr_clri(tioce_kern, &tioce_mmr->ce_ure_page_map, in tioce_kern_init()
775 tioce_mmr_seti(tioce_kern, &tioce_mmr->ce_ure_page_map, in tioce_kern_init()
777 ps = tioce_kern->ce_ate3240_pagesize = KB(256); in tioce_kern_init()
780 tioce_kern->ce_ate40_shadow[i] = 0; in tioce_kern_init()
781 tioce_mmr_storei(tioce_kern, &tioce_mmr->ce_ure_ate40[i], 0); in tioce_kern_init()
785 tioce_kern->ce_ate3240_shadow[i] = 0; in tioce_kern_init()
786 tioce_mmr_storei(tioce_kern, &tioce_mmr->ce_ure_ate3240[i], 0); in tioce_kern_init()
818 * prefetch mem base/limit. The tioce ppb's have 64-bit in tioce_kern_init()
849 * tioce_force_interrupt - implement altix force_interrupt() backend for CE
850 * @sn_irq_info: sn asic irq that we need an interrupt generated for
853 * force a secondary interrupt to be generated. This is to work around an
855 * interrupt to be lost.
866 if (!sn_irq_info->irq_bridge) in tioce_force_interrupt()
869 if (sn_irq_info->irq_bridge_type != PCIIO_ASIC_TYPE_TIOCE) in tioce_force_interrupt()
872 pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo; in tioce_force_interrupt()
876 ce_common = (struct tioce_common *)pcidev_info->pdi_pcibus_info; in tioce_force_interrupt()
877 ce_mmr = (struct tioce __iomem *)ce_common->ce_pcibus.bs_base; in tioce_force_interrupt()
878 ce_kern = (struct tioce_kernel *)ce_common->ce_kernel_private; in tioce_force_interrupt()
881 * TIOCE Rev A workaround (PV 945826), force an interrupt by writing in tioce_force_interrupt()
884 if (ce_common->ce_rev == TIOCE_REV_A) { in tioce_force_interrupt()
885 u64 int_bit_mask = (1ULL << sn_irq_info->irq_int_bit); in tioce_force_interrupt()
888 tioce_mmr_load(ce_kern, &ce_mmr->ce_adm_int_status, &status); in tioce_force_interrupt()
890 u64 force_irq = (1 << 8) | sn_irq_info->irq_irq; in tioce_force_interrupt()
891 u64 ctalk = sn_irq_info->irq_xtalkaddr; in tioce_force_interrupt()
903 * irq_int_bit is originally set up by prom, and holds the interrupt in tioce_force_interrupt()
910 switch (sn_irq_info->irq_int_bit) { in tioce_force_interrupt()
938 tioce_mmr_storei(ce_kern, &ce_mmr->ce_adm_force_int, force_int_val); in tioce_force_interrupt()
942 * tioce_target_interrupt - implement set_irq_affinity for tioce resident
947 * Given an sn_irq_info, set the associated CE device's interrupt destination
948 * register. Since the interrupt destination registers are on a per-ce-slot
962 pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo; in tioce_target_interrupt()
966 ce_common = (struct tioce_common *)pcidev_info->pdi_pcibus_info; in tioce_target_interrupt()
967 ce_mmr = (struct tioce __iomem *)ce_common->ce_pcibus.bs_base; in tioce_target_interrupt()
968 ce_kern = (struct tioce_kernel *)ce_common->ce_kernel_private; in tioce_target_interrupt()
970 bit = sn_irq_info->irq_int_bit; in tioce_target_interrupt()
972 tioce_mmr_seti(ce_kern, &ce_mmr->ce_adm_int_mask, (1UL << bit)); in tioce_target_interrupt()
973 vector = (u64)sn_irq_info->irq_irq << INTR_VECTOR_SHFT; in tioce_target_interrupt()
974 vector |= sn_irq_info->irq_xtalkaddr; in tioce_target_interrupt()
975 tioce_mmr_storei(ce_kern, &ce_mmr->ce_adm_int_dest[bit], vector); in tioce_target_interrupt()
976 tioce_mmr_clri(ce_kern, &ce_mmr->ce_adm_int_mask, (1UL << bit)); in tioce_target_interrupt()
982 * tioce_bus_fixup - perform final PCI fixup for a TIO CE bus
986 * space. Allocates and initializes a kernel-only area for a given CE,
1008 tioce_common->ce_pcibus.bs_base = (unsigned long) in tioce_bus_fixup()
1009 ioremap(REGION_OFFSET(tioce_common->ce_pcibus.bs_base), in tioce_bus_fixup()
1020 * interrupt handler. in tioce_bus_fixup()
1023 tioce_mmr = (struct tioce __iomem *)tioce_common->ce_pcibus.bs_base; in tioce_bus_fixup()
1024 tioce_mmr_seti(tioce_kern, &tioce_mmr->ce_adm_int_status_alias, ~0ULL); in tioce_bus_fixup()
1025 tioce_mmr_seti(tioce_kern, &tioce_mmr->ce_adm_error_summary_alias, in tioce_bus_fixup()
1027 tioce_mmr_seti(tioce_kern, &tioce_mmr->ce_dre_comp_err_addr, 0ULL); in tioce_bus_fixup()
1037 tioce_common->ce_pcibus.bs_persist_segment, in tioce_bus_fixup()
1038 tioce_common->ce_pcibus.bs_persist_busnum); in tioce_bus_fixup()
1054 * tioce_init_provider - init SN PCI provider ops for TIO CE