Lines Matching +full:reg +full:- +full:names
6 * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
14 #define HUB_NUM_BIG_WINDOW (IIO_NUM_ITTES - 1)
30 #define IIO_IGFX0 0x00400140 /* IO Graphics Node-Widget Map 0 */
31 #define IIO_IGFX1 0x00400148 /* IO Graphics Node-Widget Map 1 */
266 * Description: This is a read-write enabled register. It controls *
321 * Description: A write to this register of the 64-bit value *
383 * disabled. These fields assume that 0=TNUM=7 (i.e., Bridge-centric *
454 * Description: All II-detected non-BTE error interrupts are *
488 * write-responses are converted to graphics credits and returned to *
510 * write-responses are converted to graphics credits and returned to *
558 * registers. Each register maps a Shub Big Window to a 48-bit *
560 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
567 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this *
569 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
577 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> *
596 * registers. Each register maps a Shub Big Window to a 48-bit *
598 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
605 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this *
607 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
615 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> *
634 * registers. Each register maps a Shub Big Window to a 48-bit *
636 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
643 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this *
645 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
653 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> *
672 * registers. Each register maps a SHub Big Window to a 48-bit *
674 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
681 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this *
683 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
691 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> *
710 * registers. Each register maps a SHub Big Window to a 48-bit *
712 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
719 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this *
721 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
729 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> *
748 * registers. Each register maps a Shub Big Window to a 48-bit *
750 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
757 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this *
759 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
767 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> *
786 * registers. Each register maps a Shub Big Window to a 48-bit *
788 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
795 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this *
797 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
805 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> *
1543 * A write to this register of the 56-bit value "Pup+Bun" will cause *
2435 * The Shub DEBUG unit provides a 3-bit selection signal to the *
2436 * II core and a 3-bit selection signal to the fsbclk domain in the II *
2482 * address to be loaded in bits 39:0 is the 40-bit TRex+ physical *
2485 * transfers are always cacheline-aligned. *
2501 * address to be loaded in bits 39:0 is the 40-bit TRex+ physical *
2504 * transfers are always cacheline-aligned. *
2605 * address to be loaded in bits 39:0 is the 40-bit TRex+ physical *
2608 * transfers are always cacheline-aligned. *
2624 * address to be loaded in bits 39:0 is the 40-bit TRex+ physical *
2627 * transfers are always cacheline-aligned. *
2819 * Slightly friendlier names for some common registers.
2853 #define IIO_WIDPRTE_A(x) IIO_PRTE_A(((x) - 8)) /* widget ID to its PRTE num */
2854 #define IIO_WIDPRTE_B(x) IIO_PRTE_B(((x) - 8)) /* widget ID to its PRTE num */
2868 /* BTE register names */
2876 #define IIO_BTE_OFF_1 (IIO_IBLS_1 - IIO_IBLS_0) /* Offset from base to BTE 1 */
2880 #define BTEOFF_SRC (IIO_BTE_SRC_0 - IIO_BTE_STAT_0)
2881 #define BTEOFF_DEST (IIO_BTE_DEST_0 - IIO_BTE_STAT_0)
2882 #define BTEOFF_CTRL (IIO_BTE_CTRL_0 - IIO_BTE_STAT_0)
2883 #define BTEOFF_NOTIFY (IIO_BTE_NOTIFY_0 - IIO_BTE_STAT_0)
2884 #define BTEOFF_INT (IIO_BTE_INT_0 - IIO_BTE_STAT_0)
2886 /* names used in shub diags */
2894 * 0, 8 - 0xF
2898 (_x) - (HUB_WIDGET_ID_MIN-1)) << 3) )
2902 #define IIO_IGFX_W_NUM_MASK ((1<<IIO_IGFX_W_NUM_BITS)-1)
2905 #define IIO_IGFX_PI_NUM_MASK ((1<<IIO_IGFX_PI_NUM_BITS)-1)
2908 #define IIO_IGFX_N_NUM_MASK ((1<<IIO_IGFX_N_NUM_BITS)-1)
2911 #define IIO_IGFX_P_NUM_MASK ((1<<IIO_IGFX_P_NUM_BITS)-1)
2953 #define HUB_NUM_BIG_WINDOW (IIO_NUM_ITTES - 1)
2972 /* XXX - This is now tuneable:
3118 #define IECLR_SPUR_RD_HDR (1UL << 29) /* clear valid bit in ixss reg */
3121 #define IECLR_CRAZY (1UL << 16) /* clear crazy bit in wstat reg */
3122 #define IECLR_PRB_F (1UL << 15) /* clear err bit in PRB_F reg */
3123 #define IECLR_PRB_E (1UL << 14) /* clear err bit in PRB_E reg */
3124 #define IECLR_PRB_D (1UL << 13) /* clear err bit in PRB_D reg */
3125 #define IECLR_PRB_C (1UL << 12) /* clear err bit in PRB_C reg */
3126 #define IECLR_PRB_B (1UL << 11) /* clear err bit in PRB_B reg */
3127 #define IECLR_PRB_A (1UL << 10) /* clear err bit in PRB_A reg */
3128 #define IECLR_PRB_9 (1UL << 9) /* clear err bit in PRB_9 reg */
3129 #define IECLR_PRB_8 (1UL << 8) /* clear err bit in PRB_8 reg */
3130 #define IECLR_PRB_0 (1UL << 0) /* clear err bit in PRB_0 reg */
3173 * Easy access macros for CRBs, all 5 registers (A-E)
3222 #define d_bteaddr ii_icrb0_d_fld_s.id_pa_be /* ic_pa_be fld has 2 names */
3223 #define d_benable ii_icrb0_d_fld_s.id_pa_be /* ic_pa_be fld has 2 names */
3278 #define IIO_IIDEM_WIDGETDEV_MASK(w, d) ((u64)(1ULL << (8 * ((w) - 8) + (d))))