Lines Matching full:d
25 move.d CONFIG_ETRAX_DEF_R_WAITSTATES, $r0
26 move.d $r0, [R_WAITSTATES]
28 move.d CONFIG_ETRAX_DEF_R_BUS_CONFIG, $r0
29 move.d $r0, [R_BUS_CONFIG]
32 move.d CONFIG_ETRAX_DEF_R_DRAM_CONFIG, $r0
33 move.d $r0, [R_DRAM_CONFIG]
35 move.d CONFIG_ETRAX_DEF_R_DRAM_TIMING, $r0
36 move.d $r0, [R_DRAM_TIMING]
45 move.d CONFIG_ETRAX_DEF_R_SDRAM_CONFIG, $r0
46 move.d $r0, [R_SDRAM_CONFIG]
55 move.d CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r2
56 and.d 0x00ff0000, $r2
60 move.d 0x40, $r2 ; Assume 32 bits and CAS latency = 2
61 move.d CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r1
62 move.d $r1, $r3
63 and.d 0x03, $r1 ; Get CAS latency
64 and.d 0x1000, $r3 ; 50 or 100 MHz?
68 cmp.d 0x00, $r1 ; CAS latency = 2?
71 or.d 0x20, $r2 ; CAS latency = 3
75 cmp.d 0x01, $r1 ; CAS latency = 2?
78 or.d 0x20, $r2 ; CAS latency = 3
80 move.d CONFIG_ETRAX_DEF_R_SDRAM_CONFIG, $r1
81 and.d 0x800000, $r1 ; DRAM width is bit 23
88 move.d CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r1
89 and.d 0x8000f9ff, $r1 ; Make sure mrs data and command is 0
90 or.d 0x80000000, $r1 ; Make sure sdram enable bit is set
91 move.d $r1, $r5
92 or.d 0x0000c000, $r1 ; ref = disable
94 or.d $r2, $r1
95 move.d $r1, [R_SDRAM_TIMING]
98 move.d 10000, $r2
103 move.d _sdram_commands_start, $r2
104 and.d 0x000fffff, $r2 ; Make sure commands are read from flash
105 move.d _sdram_commands_end, $r3
106 and.d 0x000fffff, $r3
107 1: clear.d $r4
110 or.d $r1, $r4
111 move.d $r4, [R_SDRAM_TIMING]
117 cmp.d $r2, $r3
120 move.d $r5, [R_SDRAM_TIMING]