Lines Matching +full:interrupt +full:- +full:map +full:- +full:mask
2 * Support for C64x+ Megamodule Interrupt Controller
12 #include <linux/interrupt.h>
19 #include <asm/megamod-pic.h>
27 * Megamodule Interrupt Controller register layout
72 u32 __iomem *evtmask = &pic->regs->evtmask[src / 32]; in mask_megamod()
74 raw_spin_lock(&pic->lock); in mask_megamod()
76 raw_spin_unlock(&pic->lock); in mask_megamod()
83 u32 __iomem *evtmask = &pic->regs->evtmask[src / 32]; in unmask_megamod()
85 raw_spin_lock(&pic->lock); in unmask_megamod()
87 raw_spin_unlock(&pic->lock); in unmask_megamod()
105 pic = cascade->pic; in megamod_irq_cascade()
106 idx = cascade->index; in megamod_irq_cascade()
108 while ((events = soc_readl(&pic->regs->mevtflag[idx])) != 0) { in megamod_irq_cascade()
111 irq = irq_linear_revmap(pic->irqhost, idx * 32 + n); in megamod_irq_cascade()
113 soc_writel(1 << n, &pic->regs->evtclr[idx]); in megamod_irq_cascade()
122 struct megamod_pic *pic = h->host_data; in megamod_map()
127 if (pic->output_to_irq[i] == hw) in megamod_map()
128 return -1; in megamod_map()
152 .map = megamod_map,
162 pic->output_to_irq[output] = IRQ_UNMAPPED; in set_megamod_mux()
170 val = soc_readl(&pic->regs->intmux[index]); in set_megamod_mux()
173 soc_writel(val, &pic->regs->intmux[index]); in set_megamod_mux()
179 * The MUX map is an array of up to 12 cells; one for each usable core priority
180 * interrupt. The value of a given cell is the megamodule interrupt source
184 * values are 4 - ((NR_COMBINERS * 32) - 1). Note that the combined interrupt
185 * sources (0 - 3) are not allowed to be mapped through this property. They
187 * value of zero as a "do not map" placeholder.
192 struct device_node *np = pic->irqhost->of_node; in parse_priority_map()
193 const __be32 *map; in parse_priority_map() local
197 map = of_get_property(np, "ti,c64x+megamod-pic-mux", &maplen); in parse_priority_map()
198 if (map) { in parse_priority_map()
204 val = be32_to_cpup(map); in parse_priority_map()
207 ++map; in parse_priority_map()
222 pr_err("%s: Could not alloc PIC structure.\n", np->full_name); in init_megamod_pic()
226 pic->irqhost = irq_alloc_host(np, IRQ_HOST_MAP_LINEAR, in init_megamod_pic()
229 if (!pic->irqhost) { in init_megamod_pic()
230 pr_err("%s: Could not alloc host.\n", np->full_name); in init_megamod_pic()
234 pic->irqhost->host_data = pic; in init_megamod_pic()
236 raw_spin_lock_init(&pic->lock); in init_megamod_pic()
238 pic->regs = of_iomap(np, 0); in init_megamod_pic()
239 if (!pic->regs) { in init_megamod_pic()
240 pr_err("%s: Could not map registers.\n", np->full_name); in init_megamod_pic()
244 /* Initialize MUX map */ in init_megamod_pic()
252 * These cascades can be from the combined interrupt sources or for in init_megamod_pic()
253 * individual interrupt sources. The "interrupts" property only in init_megamod_pic()
256 * as their interrupt parent. in init_megamod_pic()
265 * We count on the core priority interrupts (4 - 15) being in init_megamod_pic()
270 pr_err("%s: combiner-%d virq %d out of range!\n", in init_megamod_pic()
271 np->full_name, i, irq); in init_megamod_pic()
276 mapping[irq - 4] = i; in init_megamod_pic()
278 pr_debug("%s: combiner-%d cascading to virq %d\n", in init_megamod_pic()
279 np->full_name, i, irq); in init_megamod_pic()
284 /* mask and clear all events in combiner */ in init_megamod_pic()
285 soc_writel(~0, &pic->regs->evtmask[i]); in init_megamod_pic()
286 soc_writel(~0, &pic->regs->evtclr[i]); in init_megamod_pic()
296 np->full_name, mapping[i], i + 4); in init_megamod_pic()
311 * Return -1 if no events active.
316 u32 mask; in get_exception() local
319 mask = soc_readl(&mm_pic->regs->mexpflag[i]); in get_exception()
320 if (mask) { in get_exception()
321 bit = __ffs(mask); in get_exception()
322 soc_writel(1 << bit, &mm_pic->regs->evtclr[i]); in get_exception()
326 return -1; in get_exception()
331 soc_writel(val, &mm_pic->regs->evtasrt); in assert_event()
338 np = of_find_compatible_node(NULL, NULL, "ti,c64x+megamod-pic"); in megamod_pic_init()