Lines Matching +full:interrupt +full:- +full:map +full:- +full:mask
2 * Copyright 2005-2010 Analog Devices Inc.
4 * Licensed under the ADI BSD license or the GPL-2 (or later)
11 /* System MMR Register Map */
14 /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
16 #define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */
17 #define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */
18 #define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
19 #define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */
20 #define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
29 /* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
33 #define SIC_IMASK0 0xFFC0010C /* SIC Interrupt Mask register 0 */
34 #define SIC_IMASK1 0xFFC00110 /* SIC Interrupt Mask register 1 */
35 #define SIC_IAR0 0xFFC00124 /* SIC Interrupt Assignment Register 0 */
36 #define SIC_IAR1 0xFFC00128 /* SIC Interrupt Assignment Register 1 */
37 #define SIC_IAR2 0xFFC0012C /* SIC Interrupt Assignment Register 2 */
38 #define SIC_IAR3 0xFFC00130 /* SIC Interrupt Assignment Register 3 */
39 #define SIC_IAR4 0xFFC00134 /* SIC Interrupt Assignment Register 4 */
40 #define SIC_IAR5 0xFFC00138 /* SIC Interrupt Assignment Register 5 */
41 #define SIC_IAR6 0xFFC0013C /* SIC Interrupt Assignment Register 6 */
42 #define SIC_IAR7 0xFFC00140 /* SIC Interrupt Assignment Register 7 */
43 #define SIC_ISR0 0xFFC00114 /* SIC Interrupt Status register 0 */
44 #define SIC_ISR1 0xFFC00118 /* SIC Interrupt Status register 1 */
45 #define SIC_IWR0 0xFFC0011C /* SIC Interrupt Wakeup-Enable register 0 */
46 #define SIC_IWR1 0xFFC00120 /* SIC Interrupt Wakeup-Enable register 1 */
48 /* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */
52 #define SICB_IMASK0 0xFFC0110C /* SIC Interrupt Mask register 0 */
53 #define SICB_IMASK1 0xFFC01110 /* SIC Interrupt Mask register 1 */
54 #define SICB_IAR0 0xFFC01124 /* SIC Interrupt Assignment Register 0 */
55 #define SICB_IAR1 0xFFC01128 /* SIC Interrupt Assignment Register 1 */
56 #define SICB_IAR2 0xFFC0112C /* SIC Interrupt Assignment Register 2 */
57 #define SICB_IAR3 0xFFC01130 /* SIC Interrupt Assignment Register 3 */
58 #define SICB_IAR4 0xFFC01134 /* SIC Interrupt Assignment Register 4 */
59 #define SICB_IAR5 0xFFC01138 /* SIC Interrupt Assignment Register 5 */
60 #define SICB_IAR6 0xFFC0113C /* SIC Interrupt Assignment Register 6 */
61 #define SICB_IAR7 0xFFC01140 /* SIC Interrupt Assignment Register 7 */
62 #define SICB_ISR0 0xFFC01114 /* SIC Interrupt Status register 0 */
63 #define SICB_ISR1 0xFFC01118 /* SIC Interrupt Status register 1 */
64 #define SICB_IWR0 0xFFC0111C /* SIC Interrupt Wakeup-Enable register 0 */
65 #define SICB_IWR1 0xFFC01120 /* SIC Interrupt Wakeup-Enable register 1 */
67 /* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */
72 /* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */
77 /* UART Controller (0xFFC00400 - 0xFFC004FF) */
85 #define BFIN_UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
86 #define BFIN_UART_IER 0xFFC00404 /* Interrupt Enable Register */
87 #define BFIN_UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
88 #define BFIN_UART_IIR 0xFFC00408 /* Interrupt Identification Register */
96 /* SPI Controller (0xFFC00500 - 0xFFC005FF) */
106 /* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */
151 /* Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) */
176 /* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */
181 #define FIO0_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Data register */
182 #define FIO0_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Clear register */
183 #define FIO0_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Set register */
184 #define FIO0_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Toggle register */
185 #define FIO0_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Data register */
186 #define FIO0_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Clear register */
187 #define FIO0_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Set register */
188 #define FIO0_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Toggle register */
191 #define FIO0_EDGE 0xFFC00738 /* Flag Interrupt Sensitivity register */
195 /* Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF) */
196 #define FIO1_FLAG_D 0xFFC01500 /* Flag Data register (mask used to directly */
199 #define FIO1_FLAG_T 0xFFC0150C /* Flag Toggle register (mask used to */
200 #define FIO1_MASKA_D 0xFFC01510 /* Flag Mask Interrupt A Data register */
201 #define FIO1_MASKA_C 0xFFC01514 /* Flag Mask Interrupt A Clear register */
202 #define FIO1_MASKA_S 0xFFC01518 /* Flag Mask Interrupt A Set register */
203 #define FIO1_MASKA_T 0xFFC0151C /* Flag Mask Interrupt A Toggle register */
204 #define FIO1_MASKB_D 0xFFC01520 /* Flag Mask Interrupt B Data register */
205 #define FIO1_MASKB_C 0xFFC01524 /* Flag Mask Interrupt B Clear register */
206 #define FIO1_MASKB_S 0xFFC01528 /* Flag Mask Interrupt B Set register */
207 #define FIO1_MASKB_T 0xFFC0152C /* Flag Mask Interrupt B Toggle register */
210 #define FIO1_EDGE 0xFFC01538 /* Flag Interrupt Sensitivity register */
214 /* Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF) */
215 #define FIO2_FLAG_D 0xFFC01700 /* Flag Data register (mask used to directly */
218 #define FIO2_FLAG_T 0xFFC0170C /* Flag Toggle register (mask used to */
219 #define FIO2_MASKA_D 0xFFC01710 /* Flag Mask Interrupt A Data register */
220 #define FIO2_MASKA_C 0xFFC01714 /* Flag Mask Interrupt A Clear register */
221 #define FIO2_MASKA_S 0xFFC01718 /* Flag Mask Interrupt A Set register */
222 #define FIO2_MASKA_T 0xFFC0171C /* Flag Mask Interrupt A Toggle register */
223 #define FIO2_MASKB_D 0xFFC01720 /* Flag Mask Interrupt B Data register */
224 #define FIO2_MASKB_C 0xFFC01724 /* Flag Mask Interrupt B Clear register */
225 #define FIO2_MASKB_S 0xFFC01728 /* Flag Mask Interrupt B Set register */
226 #define FIO2_MASKB_T 0xFFC0172C /* Flag Mask Interrupt B Toggle register */
229 #define FIO2_EDGE 0xFFC01738 /* Flag Interrupt Sensitivity register */
233 /* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
246 #define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
247 #define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
248 #define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
249 #define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
250 #define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
251 #define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
252 #define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
253 #define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
254 #define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
255 #define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
257 /* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
270 #define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
271 #define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
272 #define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
273 #define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
274 #define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
275 #define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
276 #define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
277 #define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
278 #define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
279 #define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
281 /* Asynchronous Memory Controller - External Bus Interface Unit */
286 /* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
292 /* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF) */
299 /*Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF) */
312 /* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */
324 #define DMA1_0_IRQ_STATUS 0xFFC01C28 /* DMA1 Channel 0 Interrupt/Status Register */
325 #define DMA1_0_PERIPHERAL_MAP 0xFFC01C2C /* DMA1 Channel 0 Peripheral Map Register */
338 #define DMA1_1_IRQ_STATUS 0xFFC01C68 /* DMA1 Channel 1 Interrupt/Status Register */
339 #define DMA1_1_PERIPHERAL_MAP 0xFFC01C6C /* DMA1 Channel 1 Peripheral Map Register */
352 #define DMA1_2_IRQ_STATUS 0xFFC01CA8 /* DMA1 Channel 2 Interrupt/Status Register */
353 #define DMA1_2_PERIPHERAL_MAP 0xFFC01CAC /* DMA1 Channel 2 Peripheral Map Register */
366 #define DMA1_3_IRQ_STATUS 0xFFC01CE8 /* DMA1 Channel 3 Interrupt/Status Register */
367 #define DMA1_3_PERIPHERAL_MAP 0xFFC01CEC /* DMA1 Channel 3 Peripheral Map Register */
380 #define DMA1_4_IRQ_STATUS 0xFFC01D28 /* DMA1 Channel 4 Interrupt/Status Register */
381 #define DMA1_4_PERIPHERAL_MAP 0xFFC01D2C /* DMA1 Channel 4 Peripheral Map Register */
394 #define DMA1_5_IRQ_STATUS 0xFFC01D68 /* DMA1 Channel 5 Interrupt/Status Register */
395 #define DMA1_5_PERIPHERAL_MAP 0xFFC01D6C /* DMA1 Channel 5 Peripheral Map Register */
408 #define DMA1_6_IRQ_STATUS 0xFFC01DA8 /* DMA1 Channel 6 Interrupt/Status Register */
409 #define DMA1_6_PERIPHERAL_MAP 0xFFC01DAC /* DMA1 Channel 6 Peripheral Map Register */
422 #define DMA1_7_IRQ_STATUS 0xFFC01DE8 /* DMA1 Channel 7 Interrupt/Status Register */
423 #define DMA1_7_PERIPHERAL_MAP 0xFFC01DEC /* DMA1 Channel 7 Peripheral Map Register */
436 #define DMA1_8_IRQ_STATUS 0xFFC01E28 /* DMA1 Channel 8 Interrupt/Status Register */
437 #define DMA1_8_PERIPHERAL_MAP 0xFFC01E2C /* DMA1 Channel 8 Peripheral Map Register */
450 #define DMA1_9_IRQ_STATUS 0xFFC01E68 /* DMA1 Channel 9 Interrupt/Status Register */
451 #define DMA1_9_PERIPHERAL_MAP 0xFFC01E6C /* DMA1 Channel 9 Peripheral Map Register */
464 #define DMA1_10_IRQ_STATUS 0xFFC01EA8 /* DMA1 Channel 10 Interrupt/Status Register */
465 #define DMA1_10_PERIPHERAL_MAP 0xFFC01EAC /* DMA1 Channel 10 Peripheral Map Register */
478 #define DMA1_11_IRQ_STATUS 0xFFC01EE8 /* DMA1 Channel 11 Interrupt/Status Register */
479 #define DMA1_11_PERIPHERAL_MAP 0xFFC01EEC /* DMA1 Channel 11 Peripheral Map Register */
481 /* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */
485 #define MDMA_D2_X_COUNT 0xFFC01F10 /*MemDMA1 Stream 0 Destination Inner-Loop Count */
486 #define MDMA_D2_Y_COUNT 0xFFC01F18 /*MemDMA1 Stream 0 Destination Outer-Loop Count */
487 #define MDMA_D2_X_MODIFY 0xFFC01F14 /*MemDMA1 Stream 0 Dest Inner-Loop Address-Increment */
488 #define MDMA_D2_Y_MODIFY 0xFFC01F1C /*MemDMA1 Stream 0 Dest Outer-Loop Address-Increment */
491 #define MDMA_D2_CURR_X_COUNT 0xFFC01F30 /*MemDMA1 Stream 0 Dest Current Inner-Loop Count */
492 #define MDMA_D2_CURR_Y_COUNT 0xFFC01F38 /*MemDMA1 Stream 0 Dest Current Outer-Loop Count */
493 #define MDMA_D2_IRQ_STATUS 0xFFC01F28 /*MemDMA1 Stream 0 Destination Interrupt/Status */
494 #define MDMA_D2_PERIPHERAL_MAP 0xFFC01F2C /*MemDMA1 Stream 0 Destination Peripheral Map */
499 #define MDMA_S2_X_COUNT 0xFFC01F50 /*MemDMA1 Stream 0 Source Inner-Loop Count */
500 #define MDMA_S2_Y_COUNT 0xFFC01F58 /*MemDMA1 Stream 0 Source Outer-Loop Count */
501 #define MDMA_S2_X_MODIFY 0xFFC01F54 /*MemDMA1 Stream 0 Source Inner-Loop Address-Increment */
502 #define MDMA_S2_Y_MODIFY 0xFFC01F5C /*MemDMA1 Stream 0 Source Outer-Loop Address-Increment */
505 #define MDMA_S2_CURR_X_COUNT 0xFFC01F70 /*MemDMA1 Stream 0 Source Current Inner-Loop Count */
506 #define MDMA_S2_CURR_Y_COUNT 0xFFC01F78 /*MemDMA1 Stream 0 Source Current Outer-Loop Count */
507 #define MDMA_S2_IRQ_STATUS 0xFFC01F68 /*MemDMA1 Stream 0 Source Interrupt/Status */
508 #define MDMA_S2_PERIPHERAL_MAP 0xFFC01F6C /*MemDMA1 Stream 0 Source Peripheral Map */
513 #define MDMA_D3_X_COUNT 0xFFC01F90 /*MemDMA1 Stream 1 Destination Inner-Loop Count */
514 #define MDMA_D3_Y_COUNT 0xFFC01F98 /*MemDMA1 Stream 1 Destination Outer-Loop Count */
515 #define MDMA_D3_X_MODIFY 0xFFC01F94 /*MemDMA1 Stream 1 Dest Inner-Loop Address-Increment */
516 #define MDMA_D3_Y_MODIFY 0xFFC01F9C /*MemDMA1 Stream 1 Dest Outer-Loop Address-Increment */
519 #define MDMA_D3_CURR_X_COUNT 0xFFC01FB0 /*MemDMA1 Stream 1 Dest Current Inner-Loop Count */
520 #define MDMA_D3_CURR_Y_COUNT 0xFFC01FB8 /*MemDMA1 Stream 1 Dest Current Outer-Loop Count */
521 #define MDMA_D3_IRQ_STATUS 0xFFC01FA8 /*MemDMA1 Stream 1 Dest Interrupt/Status */
522 #define MDMA_D3_PERIPHERAL_MAP 0xFFC01FAC /*MemDMA1 Stream 1 Dest Peripheral Map */
527 #define MDMA_S3_X_COUNT 0xFFC01FD0 /*MemDMA1 Stream 1 Source Inner-Loop Count */
528 #define MDMA_S3_Y_COUNT 0xFFC01FD8 /*MemDMA1 Stream 1 Source Outer-Loop Count */
529 #define MDMA_S3_X_MODIFY 0xFFC01FD4 /*MemDMA1 Stream 1 Source Inner-Loop Address-Increment */
530 #define MDMA_S3_Y_MODIFY 0xFFC01FDC /*MemDMA1 Stream 1 Source Outer-Loop Address-Increment */
533 #define MDMA_S3_CURR_X_COUNT 0xFFC01FF0 /*MemDMA1 Stream 1 Source Current Inner-Loop Count */
534 #define MDMA_S3_CURR_Y_COUNT 0xFFC01FF8 /*MemDMA1 Stream 1 Source Current Outer-Loop Count */
535 #define MDMA_S3_IRQ_STATUS 0xFFC01FE8 /*MemDMA1 Stream 1 Source Interrupt/Status */
536 #define MDMA_S3_PERIPHERAL_MAP 0xFFC01FEC /*MemDMA1 Stream 1 Source Peripheral Map */
538 /* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */
550 #define DMA2_0_IRQ_STATUS 0xFFC00C28 /* DMA2 Channel 0 Interrupt/Status Register */
551 #define DMA2_0_PERIPHERAL_MAP 0xFFC00C2C /* DMA2 Channel 0 Peripheral Map Register */
564 #define DMA2_1_IRQ_STATUS 0xFFC00C68 /* DMA2 Channel 1 Interrupt/Status Register */
565 #define DMA2_1_PERIPHERAL_MAP 0xFFC00C6C /* DMA2 Channel 1 Peripheral Map Register */
578 #define DMA2_2_IRQ_STATUS 0xFFC00CA8 /* DMA2 Channel 2 Interrupt/Status Register */
579 #define DMA2_2_PERIPHERAL_MAP 0xFFC00CAC /* DMA2 Channel 2 Peripheral Map Register */
592 #define DMA2_3_IRQ_STATUS 0xFFC00CE8 /* DMA2 Channel 3 Interrupt/Status Register */
593 #define DMA2_3_PERIPHERAL_MAP 0xFFC00CEC /* DMA2 Channel 3 Peripheral Map Register */
606 #define DMA2_4_IRQ_STATUS 0xFFC00D28 /* DMA2 Channel 4 Interrupt/Status Register */
607 #define DMA2_4_PERIPHERAL_MAP 0xFFC00D2C /* DMA2 Channel 4 Peripheral Map Register */
620 #define DMA2_5_IRQ_STATUS 0xFFC00D68 /* DMA2 Channel 5 Interrupt/Status Register */
621 #define DMA2_5_PERIPHERAL_MAP 0xFFC00D6C /* DMA2 Channel 5 Peripheral Map Register */
634 #define DMA2_6_IRQ_STATUS 0xFFC00DA8 /* DMA2 Channel 6 Interrupt/Status Register */
635 #define DMA2_6_PERIPHERAL_MAP 0xFFC00DAC /* DMA2 Channel 6 Peripheral Map Register */
648 #define DMA2_7_IRQ_STATUS 0xFFC00DE8 /* DMA2 Channel 7 Interrupt/Status Register */
649 #define DMA2_7_PERIPHERAL_MAP 0xFFC00DEC /* DMA2 Channel 7 Peripheral Map Register */
662 #define DMA2_8_IRQ_STATUS 0xFFC00E28 /* DMA2 Channel 8 Interrupt/Status Register */
663 #define DMA2_8_PERIPHERAL_MAP 0xFFC00E2C /* DMA2 Channel 8 Peripheral Map Register */
676 #define DMA2_9_IRQ_STATUS 0xFFC00E68 /* DMA2 Channel 9 Interrupt/Status Register */
677 #define DMA2_9_PERIPHERAL_MAP 0xFFC00E6C /* DMA2 Channel 9 Peripheral Map Register */
690 #define DMA2_10_IRQ_STATUS 0xFFC00EA8 /* DMA2 Channel 10 Interrupt/Status Register */
691 #define DMA2_10_PERIPHERAL_MAP 0xFFC00EAC /* DMA2 Channel 10 Peripheral Map Register */
704 #define DMA2_11_IRQ_STATUS 0xFFC00EE8 /* DMA2 Channel 11 Interrupt/Status Register */
705 #define DMA2_11_PERIPHERAL_MAP 0xFFC00EEC /* DMA2 Channel 11 Peripheral Map Register */
707 /* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */
711 #define MDMA_D0_X_COUNT 0xFFC00F10 /*MemDMA2 Stream 0 Dest Inner-Loop Count register */
712 #define MDMA_D0_Y_COUNT 0xFFC00F18 /*MemDMA2 Stream 0 Dest Outer-Loop Count register */
713 #define MDMA_D0_X_MODIFY 0xFFC00F14 /*MemDMA2 Stream 0 Dest Inner-Loop Address-Increment */
714 #define MDMA_D0_Y_MODIFY 0xFFC00F1C /*MemDMA2 Stream 0 Dest Outer-Loop Address-Increment */
717 #define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /*MemDMA2 Stream 0 Dest Current Inner-Loop Count reg */
718 #define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /*MemDMA2 Stream 0 Dest Current Outer-Loop Count reg */
719 #define MDMA_D0_IRQ_STATUS 0xFFC00F28 /*MemDMA2 Stream 0 Dest Interrupt/Status Register */
720 #define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /*MemDMA2 Stream 0 Destination Peripheral Map register */
725 #define MDMA_S0_X_COUNT 0xFFC00F50 /*MemDMA2 Stream 0 Source Inner-Loop Count register */
726 #define MDMA_S0_Y_COUNT 0xFFC00F58 /*MemDMA2 Stream 0 Source Outer-Loop Count register */
727 #define MDMA_S0_X_MODIFY 0xFFC00F54 /*MemDMA2 Stream 0 Src Inner-Loop Addr-Increment reg */
728 #define MDMA_S0_Y_MODIFY 0xFFC00F5C /*MemDMA2 Stream 0 Src Outer-Loop Addr-Increment reg */
731 #define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /*MemDMA2 Stream 0 Src Current Inner-Loop Count reg */
732 #define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /*MemDMA2 Stream 0 Src Current Outer-Loop Count reg */
733 #define MDMA_S0_IRQ_STATUS 0xFFC00F68 /*MemDMA2 Stream 0 Source Interrupt/Status Register */
734 #define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /*MemDMA2 Stream 0 Source Peripheral Map register */
739 #define MDMA_D1_X_COUNT 0xFFC00F90 /*MemDMA2 Stream 1 Dest Inner-Loop Count register */
740 #define MDMA_D1_Y_COUNT 0xFFC00F98 /*MemDMA2 Stream 1 Dest Outer-Loop Count register */
741 #define MDMA_D1_X_MODIFY 0xFFC00F94 /*MemDMA2 Stream 1 Dest Inner-Loop Address-Increment */
742 #define MDMA_D1_Y_MODIFY 0xFFC00F9C /*MemDMA2 Stream 1 Dest Outer-Loop Address-Increment */
745 #define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /*MemDMA2 Stream 1 Dest Current Inner-Loop Count reg */
746 #define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /*MemDMA2 Stream 1 Dest Current Outer-Loop Count reg */
747 #define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /*MemDMA2 Stream 1 Destination Interrupt/Status Reg */
748 #define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /*MemDMA2 Stream 1 Destination Peripheral Map register */
753 #define MDMA_S1_X_COUNT 0xFFC00FD0 /*MemDMA2 Stream 1 Source Inner-Loop Count register */
754 #define MDMA_S1_Y_COUNT 0xFFC00FD8 /*MemDMA2 Stream 1 Source Outer-Loop Count register */
755 #define MDMA_S1_X_MODIFY 0xFFC00FD4 /*MemDMA2 Stream 1 Src Inner-Loop Address-Increment */
756 #define MDMA_S1_Y_MODIFY 0xFFC00FDC /*MemDMA2 Stream 1 Source Outer-Loop Address-Increment */
759 #define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /*MemDMA2 Stream 1 Source Current Inner-Loop Count */
760 #define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /*MemDMA2 Stream 1 Source Current Outer-Loop Count */
761 #define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /*MemDMA2 Stream 1 Source Interrupt/Status Register */
762 #define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /*MemDMA2 Stream 1 Source Peripheral Map register */
764 /* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */
768 #define IMDMA_D0_X_COUNT 0xFFC01810 /*IMDMA Stream 0 Destination Inner-Loop Count */
769 #define IMDMA_D0_Y_COUNT 0xFFC01818 /*IMDMA Stream 0 Destination Outer-Loop Count */
770 #define IMDMA_D0_X_MODIFY 0xFFC01814 /*IMDMA Stream 0 Dest Inner-Loop Address-Increment */
771 #define IMDMA_D0_Y_MODIFY 0xFFC0181C /*IMDMA Stream 0 Dest Outer-Loop Address-Increment */
774 #define IMDMA_D0_CURR_X_COUNT 0xFFC01830 /*IMDMA Stream 0 Destination Current Inner-Loop Count */
775 #define IMDMA_D0_CURR_Y_COUNT 0xFFC01838 /*IMDMA Stream 0 Destination Current Outer-Loop Count */
776 #define IMDMA_D0_IRQ_STATUS 0xFFC01828 /*IMDMA Stream 0 Destination Interrupt/Status */
781 #define IMDMA_S0_X_COUNT 0xFFC01850 /*IMDMA Stream 0 Source Inner-Loop Count */
782 #define IMDMA_S0_Y_COUNT 0xFFC01858 /*IMDMA Stream 0 Source Outer-Loop Count */
783 #define IMDMA_S0_X_MODIFY 0xFFC01854 /*IMDMA Stream 0 Source Inner-Loop Address-Increment */
784 #define IMDMA_S0_Y_MODIFY 0xFFC0185C /*IMDMA Stream 0 Source Outer-Loop Address-Increment */
787 #define IMDMA_S0_CURR_X_COUNT 0xFFC01870 /*IMDMA Stream 0 Source Current Inner-Loop Count */
788 #define IMDMA_S0_CURR_Y_COUNT 0xFFC01878 /*IMDMA Stream 0 Source Current Outer-Loop Count */
789 #define IMDMA_S0_IRQ_STATUS 0xFFC01868 /*IMDMA Stream 0 Source Interrupt/Status */
794 #define IMDMA_D1_X_COUNT 0xFFC01890 /*IMDMA Stream 1 Destination Inner-Loop Count */
795 #define IMDMA_D1_Y_COUNT 0xFFC01898 /*IMDMA Stream 1 Destination Outer-Loop Count */
796 #define IMDMA_D1_X_MODIFY 0xFFC01894 /*IMDMA Stream 1 Dest Inner-Loop Address-Increment */
797 #define IMDMA_D1_Y_MODIFY 0xFFC0189C /*IMDMA Stream 1 Dest Outer-Loop Address-Increment */
800 #define IMDMA_D1_CURR_X_COUNT 0xFFC018B0 /*IMDMA Stream 1 Destination Current Inner-Loop Count */
801 #define IMDMA_D1_CURR_Y_COUNT 0xFFC018B8 /*IMDMA Stream 1 Destination Current Outer-Loop Count */
802 #define IMDMA_D1_IRQ_STATUS 0xFFC018A8 /*IMDMA Stream 1 Destination Interrupt/Status */
807 #define IMDMA_S1_X_COUNT 0xFFC018D0 /*IMDMA Stream 1 Source Inner-Loop Count */
808 #define IMDMA_S1_Y_COUNT 0xFFC018D8 /*IMDMA Stream 1 Source Outer-Loop Count */
809 #define IMDMA_S1_X_MODIFY 0xFFC018D4 /*IMDMA Stream 1 Source Inner-Loop Address-Increment */
810 #define IMDMA_S1_Y_MODIFY 0xFFC018DC /*IMDMA Stream 1 Source Outer-Loop Address-Increment */
813 #define IMDMA_S1_CURR_X_COUNT 0xFFC018F0 /*IMDMA Stream 1 Source Current Inner-Loop Count */
814 #define IMDMA_S1_CURR_Y_COUNT 0xFFC018F8 /*IMDMA Stream 1 Source Current Outer-Loop Count */
815 #define IMDMA_S1_IRQ_STATUS 0xFFC018E8 /*IMDMA Stream 1 Source Interrupt/Status */
829 /* SWRST Mask */
839 /* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
849 …((IVG_number) - 7) << (((Per_number) % 8) * 4) /* Peripheral #Per_number assigned IVG #IVG_number …
856 #define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
857 #define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */
858 #define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */
863 /* x = pos 0 to 31, for 32-63 use value-32 */
876 #define DMA32 0x00000100 /* PPI 32-bit DMA Enable */
880 #define DLEN_8 0x0 /* PPI Data Length mask for DLEN=8 */
881 #define DLEN(x) (((x-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */
900 #define PCAP8 0x00000080 /* DMA 8-bit Operation Indicator */
901 #define PCAP16 0x00000100 /* DMA 16-bit Operation Indicator */
902 #define PCAP32 0x00000200 /* DMA 32-bit Operation Indicator */
905 #define PMAP 0x00007000 /* DMA Peripheral Map Field */
1101 #define B0_PEN 0x0010 /* Enable 16-bit packing Bank 0 */
1102 #define B1_PEN 0x0020 /* Enable 16-bit packing Bank 1 */
1103 #define B2_PEN 0x0040 /* Enable 16-bit packing Bank 2 */
1104 #define B3_PEN 0x0080 /* Enable 16-bit packing Bank 3 */
1108 #define AMBEN_P0 0x00000001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 …
1109 …e AMBEN_P1 0x00000002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 en…
1110 #define AMBEN_P2 0x00000003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) e…
1111 #define B0_PEN_P 0x004 /* Enable 16-bit packing Bank 0 */
1112 #define B1_PEN_P 0x005 /* Enable 16-bit packing Bank 1 */
1113 #define B2_PEN_P 0x006 /* Enable 16-bit packing Bank 2 */
1114 #define B3_PEN_P 0x007 /* Enable 16-bit packing Bank 3 */
1336 #define PUPSD 0x00200000 /*Power-up start delay */
1337 #define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh c…
1338 #define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */
1339 #define SRFS 0x01000000 /* Start SDRAM self-refresh mode */
1341 #define FBBRW 0x04000000 /* Fast back-to-back read write enable */
1392 #define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */