Lines Matching +full:multi +full:- +full:line
2 * Copyright 2007-2010 Analog Devices Inc.
4 * Licensed under the ADI BSD license or the GPL-2 (or later)
12 /* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */
23 /* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */
31 /* System Reset and Interrupt Controller (0xFFC00100 - 0xFFC00104) */
81 #define UART0_LCR 0xffc0040c /* Line Control Register */
83 #define UART0_LSR 0xffc00414 /* Line Status Register */
102 …rs are not defined in the shared file because they are not available on the ADSP-BF542 processor */
124 /* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-…
140 #define SPORT1_MCMC1 0xffc00938 /* SPORT1 Multi channel Configuration Regist…
141 #define SPORT1_MCMC2 0xffc0093c /* SPORT1 Multi channel Configuration Regist…
142 #define SPORT1_MTCS0 0xffc00940 /* SPORT1 Multi channel Transmit Select Regi…
143 #define SPORT1_MTCS1 0xffc00944 /* SPORT1 Multi channel Transmit Select Regi…
144 #define SPORT1_MTCS2 0xffc00948 /* SPORT1 Multi channel Transmit Select Regi…
145 #define SPORT1_MTCS3 0xffc0094c /* SPORT1 Multi channel Transmit Select Regi…
146 #define SPORT1_MRCS0 0xffc00950 /* SPORT1 Multi channel Receive Select Regis…
147 #define SPORT1_MRCS1 0xffc00954 /* SPORT1 Multi channel Receive Select Regis…
148 #define SPORT1_MRCS2 0xffc00958 /* SPORT1 Multi channel Receive Select Regis…
149 #define SPORT1_MRCS3 0xffc0095c /* SPORT1 Multi channel Receive Select Regis…
192 #define EBIU_DDRARCT 0xffc00aac /* DDR Auto-refresh Count Register */
460 #define UART3_LCR 0xffc0310c /* Line Control Register */
462 #define UART3_LSR 0xffc03114 /* Line Status Register */
478 #define EPPI1_LINE 0xffc01318 /* EPPI1 Samples per Line Register */
481 … 0xffc01324 /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
482 …P_AVPL 0xffc01328 /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
487 /* Port Interrupt 0 Registers (32-bit) */
493 #define PINT0_EDGE_SET 0xffc01410 /* Pin Interrupt 0 Edge-sensitivity Set Regi…
494 #define PINT0_EDGE_CLEAR 0xffc01414 /* Pin Interrupt 0 Edge-sensitivity Clear Re…
500 /* Port Interrupt 1 Registers (32-bit) */
506 #define PINT1_EDGE_SET 0xffc01440 /* Pin Interrupt 1 Edge-sensitivity Set Regi…
507 #define PINT1_EDGE_CLEAR 0xffc01444 /* Pin Interrupt 1 Edge-sensitivity Clear Re…
513 /* Port Interrupt 2 Registers (32-bit) */
519 #define PINT2_EDGE_SET 0xffc01470 /* Pin Interrupt 2 Edge-sensitivity Set Regi…
520 #define PINT2_EDGE_CLEAR 0xffc01474 /* Pin Interrupt 2 Edge-sensitivity Clear Re…
526 /* Port Interrupt 3 Registers (32-bit) */
532 #define PINT3_EDGE_SET 0xffc014a0 /* Pin Interrupt 3 Edge-sensitivity Set Regi…
533 #define PINT3_EDGE_CLEAR 0xffc014a4 /* Pin Interrupt 3 Edge-sensitivity Clear Re…
950 #define UART1_LCR 0xffc0200c /* Line Control Register */
952 #define UART1_LSR 0xffc02014 /* Line Status Register */
960 /* UART2 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-B…
987 #define SPORT2_MCMC1 0xffc02538 /* SPORT2 Multi channel Configuration Regist…
988 #define SPORT2_MCMC2 0xffc0253c /* SPORT2 Multi channel Configuration Regist…
989 #define SPORT2_MTCS0 0xffc02540 /* SPORT2 Multi channel Transmit Select Regi…
990 #define SPORT2_MTCS1 0xffc02544 /* SPORT2 Multi channel Transmit Select Regi…
991 #define SPORT2_MTCS2 0xffc02548 /* SPORT2 Multi channel Transmit Select Regi…
992 #define SPORT2_MTCS3 0xffc0254c /* SPORT2 Multi channel Transmit Select Regi…
993 #define SPORT2_MRCS0 0xffc02550 /* SPORT2 Multi channel Receive Select Regis…
994 #define SPORT2_MRCS1 0xffc02554 /* SPORT2 Multi channel Receive Select Regis…
995 #define SPORT2_MRCS2 0xffc02558 /* SPORT2 Multi channel Receive Select Regis…
996 #define SPORT2_MRCS3 0xffc0255c /* SPORT2 Multi channel Receive Select Regis…
1012 #define SPORT3_MCMC1 0xffc02638 /* SPORT3 Multi channel Configuration Regist…
1013 #define SPORT3_MCMC2 0xffc0263c /* SPORT3 Multi channel Configuration Regist…
1014 #define SPORT3_MTCS0 0xffc02640 /* SPORT3 Multi channel Transmit Select Regi…
1015 #define SPORT3_MTCS1 0xffc02644 /* SPORT3 Multi channel Transmit Select Regi…
1016 #define SPORT3_MTCS2 0xffc02648 /* SPORT3 Multi channel Transmit Select Regi…
1017 #define SPORT3_MTCS3 0xffc0264c /* SPORT3 Multi channel Transmit Select Regi…
1018 #define SPORT3_MRCS0 0xffc02650 /* SPORT3 Multi channel Receive Select Regis…
1019 #define SPORT3_MRCS1 0xffc02654 /* SPORT3 Multi channel Receive Select Regis…
1020 #define SPORT3_MRCS2 0xffc02658 /* SPORT3 Multi channel Receive Select Regis…
1021 #define SPORT3_MRCS3 0xffc0265c /* SPORT3 Multi channel Receive Select Regis…
1031 #define EPPI2_LINE 0xffc02918 /* EPPI2 Samples per Line Register */
1034 … 0xffc02924 /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
1035 …P_AVPL 0xffc02928 /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
1428 #define UART3_LCR 0xffc0310c /* Line Control Register */
1430 #define UART3_LSR 0xffc03114 /* Line Status Register */
1487 #define OTP_DATA0 0xffc04380 /* OTP/Fuse Data (OTP_DATA0-3) accesses the …
1488 #define OTP_DATA1 0xffc04384 /* OTP/Fuse Data (OTP_DATA0-3) accesses the …
1489 #define OTP_DATA2 0xffc04388 /* OTP/Fuse Data (OTP_DATA0-3) accesses the …
1490 #define OTP_DATA3 0xffc0438c /* OTP/Fuse Data (OTP_DATA0-3) accesses the …
1492 /* Handshake MDMA is not defined in the shared file because it is not available on the ADSP-BF542 p…
1496 /* and MULTI BIT READ MACROS */
1523 #define RTC 0x80 /* Real-Time Clock */
1710 #define TRFC 0x3c000 /* Auto-refresh command period */
1711 #define TRP 0x3c0000 /* Pre charge-to-active command period */
1712 #define TRAS 0x3c00000 /* Min Active-to-pre charge time */
1713 #define TRC 0x3c000000 /* Active-to-active time */
1722 #define TRCD 0xf /* Active-to-Read/write delay */
1729 #define TWTR 0xf0000000 /* Write-to-read delay */
1758 #define PASR 0x7 /* Partial array self-refresh */
1785 #define SRREQ 0x8 /* Self-refresh request */
1786 #define SRACK 0x10 /* Self-refresh acknowledge */
1809 #define ARCENABLE 0x40000 /* DDR Auto-refresh count enable */
1835 #define CRWTACOUNT 0x20000 /* Clear R/W turn-around count */
1836 #define CARCOUNT 0x40000 /* Clear auto-refresh count */
1842 /* Bit masks for (PORTx is PORTA - PORTJ) includes PORTx_FER, PORTx_SET, PORTx_CLEAR, PORTx_DIR_SET…
1861 /* Bit masks for PORTA_MUX - PORTJ_MUX */
1993 #define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
2001 #define LTERR_OVR 0x4 /* Line Track Overflow */
2002 #define LTERR_UNDR 0x8 /* Line Track Underflow */
2029 #define SIGN_EXT 0x400000 /* Sign Extension or Zero-filled / Data Split Format …
2031 #define SUBSPLT_ODD 0x1000000 /* Sub-split Odd Samples */
2037 #define DLEN_8 (0 << 15) /* 000 - 8 bits */
2038 #define DLEN_10 (1 << 15) /* 001 - 10 bits */
2039 #define DLEN_12 (2 << 15) /* 010 - 12 bits */
2040 #define DLEN_14 (3 << 15) /* 011 - 14 bits */
2041 #define DLEN_16 (4 << 15) /* 100 - 16 bits */
2042 #define DLEN_18 (5 << 15) /* 101 - 18 bits */
2043 #define DLEN_24 (6 << 15) /* 110 - 24 bits */
2066 /* The TWI bit masks fields are from the ADSP-BF538 */
2161 #define XMTDATA8 0xff /* Transmit FIFO 8-Bit Data */
2165 #define XMTDATA16 0xffff /* Transmit FIFO 16-Bit Data */
2169 #define RCVDATA8 0xff /* Receive FIFO 8-Bit Data */
2173 #define RCVDATA16 0xffff /* Receive FIFO 16-Bit Data */
2176 /* MULTI BIT MACRO ENUMERATIONS */
2181 #define BCODE_WAKEUP 0x0000 /* boot according to wake-up condition */