Lines Matching +full:interrupt +full:- +full:map +full:- +full:mask
2 * Copyright 2007-2010 Analog Devices Inc.
4 * Licensed under the ADI BSD license or the GPL-2 (or later)
12 /* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */
23 /* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */
31 /* System Reset and Interrupt Controller (0xFFC00100 - 0xFFC00104) */
39 #define SIC_IMASK0 0xffc0010c /* System Interrupt Mask Register 0 */
40 #define SIC_IMASK1 0xffc00110 /* System Interrupt Mask Register 1 */
41 #define SIC_IMASK2 0xffc00114 /* System Interrupt Mask Register 2 */
42 #define SIC_ISR0 0xffc00118 /* System Interrupt Status Register 0 */
43 #define SIC_ISR1 0xffc0011c /* System Interrupt Status Register 1 */
44 #define SIC_ISR2 0xffc00120 /* System Interrupt Status Register 2 */
45 #define SIC_IWR0 0xffc00124 /* System Interrupt Wakeup Register 0 */
46 #define SIC_IWR1 0xffc00128 /* System Interrupt Wakeup Register 1 */
47 #define SIC_IWR2 0xffc0012c /* System Interrupt Wakeup Register 2 */
48 #define SIC_IAR0 0xffc00130 /* System Interrupt Assignment Register 0 */
49 #define SIC_IAR1 0xffc00134 /* System Interrupt Assignment Register 1 */
50 #define SIC_IAR2 0xffc00138 /* System Interrupt Assignment Register 2 */
51 #define SIC_IAR3 0xffc0013c /* System Interrupt Assignment Register 3 */
52 #define SIC_IAR4 0xffc00140 /* System Interrupt Assignment Register 4 */
53 #define SIC_IAR5 0xffc00144 /* System Interrupt Assignment Register 5 */
54 #define SIC_IAR6 0xffc00148 /* System Interrupt Assignment Register 6 */
55 #define SIC_IAR7 0xffc0014c /* System Interrupt Assignment Register 7 */
56 #define SIC_IAR8 0xffc00150 /* System Interrupt Assignment Register 8 */
57 #define SIC_IAR9 0xffc00154 /* System Interrupt Assignment Register 9 */
58 #define SIC_IAR10 0xffc00158 /* System Interrupt Assignment Register 10 */
59 #define SIC_IAR11 0xffc0015c /* System Interrupt Assignment Register 11 */
70 #define RTC_ICTL 0xffc00304 /* RTC Interrupt Control Register */
71 #define RTC_ISTAT 0xffc00308 /* RTC Interrupt Status Register */
86 #define UART0_IER_SET 0xffc00420 /* Interrupt Enable Register Set */
87 #define UART0_IER_CLEAR 0xffc00424 /* Interrupt Enable Register Clear */
102 …rs are not defined in the shared file because they are not available on the ADSP-BF542 processor */
115 #define TWI0_INT_STAT 0xffc00720 /* TWI Interrupt Status Register */
116 #define TWI0_INT_MASK 0xffc00724 /* TWI Interrupt Mask Register */
124 /* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-…
192 #define EBIU_DDRARCT 0xffc00aac /* DDR Auto-refresh Count Register */
216 #define DMA0_IRQ_STATUS 0xffc00c28 /* DMA Channel 0 Interrupt/Status Register */
217 #define DMA0_PERIPHERAL_MAP 0xffc00c2c /* DMA Channel 0 Peripheral Map Register */
232 #define DMA1_IRQ_STATUS 0xffc00c68 /* DMA Channel 1 Interrupt/Status Register */
233 #define DMA1_PERIPHERAL_MAP 0xffc00c6c /* DMA Channel 1 Peripheral Map Register */
248 #define DMA2_IRQ_STATUS 0xffc00ca8 /* DMA Channel 2 Interrupt/Status Register */
249 #define DMA2_PERIPHERAL_MAP 0xffc00cac /* DMA Channel 2 Peripheral Map Register */
264 #define DMA3_IRQ_STATUS 0xffc00ce8 /* DMA Channel 3 Interrupt/Status Register */
265 #define DMA3_PERIPHERAL_MAP 0xffc00cec /* DMA Channel 3 Peripheral Map Register */
280 #define DMA4_IRQ_STATUS 0xffc00d28 /* DMA Channel 4 Interrupt/Status Register */
281 #define DMA4_PERIPHERAL_MAP 0xffc00d2c /* DMA Channel 4 Peripheral Map Register */
296 #define DMA5_IRQ_STATUS 0xffc00d68 /* DMA Channel 5 Interrupt/Status Register */
297 #define DMA5_PERIPHERAL_MAP 0xffc00d6c /* DMA Channel 5 Peripheral Map Register */
312 #define DMA6_IRQ_STATUS 0xffc00da8 /* DMA Channel 6 Interrupt/Status Register */
313 #define DMA6_PERIPHERAL_MAP 0xffc00dac /* DMA Channel 6 Peripheral Map Register */
328 #define DMA7_IRQ_STATUS 0xffc00de8 /* DMA Channel 7 Interrupt/Status Register */
329 #define DMA7_PERIPHERAL_MAP 0xffc00dec /* DMA Channel 7 Peripheral Map Register */
344 #define DMA8_IRQ_STATUS 0xffc00e28 /* DMA Channel 8 Interrupt/Status Register */
345 #define DMA8_PERIPHERAL_MAP 0xffc00e2c /* DMA Channel 8 Peripheral Map Register */
360 #define DMA9_IRQ_STATUS 0xffc00e68 /* DMA Channel 9 Interrupt/Status Register */
361 #define DMA9_PERIPHERAL_MAP 0xffc00e6c /* DMA Channel 9 Peripheral Map Register */
376 #define DMA10_IRQ_STATUS 0xffc00ea8 /* DMA Channel 10 Interrupt/Status Register …
377 #define DMA10_PERIPHERAL_MAP 0xffc00eac /* DMA Channel 10 Peripheral Map Register */
392 #define DMA11_IRQ_STATUS 0xffc00ee8 /* DMA Channel 11 Interrupt/Status Register …
393 #define DMA11_PERIPHERAL_MAP 0xffc00eec /* DMA Channel 11 Peripheral Map Register */
408 #define MDMA_D0_IRQ_STATUS 0xffc00f28 /* Memory DMA Stream 0 Destination Interrupt…
409 … MDMA_D0_PERIPHERAL_MAP 0xffc00f2c /* Memory DMA Stream 0 Destination Peripheral Map Register */
421 #define MDMA_S0_IRQ_STATUS 0xffc00f68 /* Memory DMA Stream 0 Source Interrupt/Stat…
422 #define MDMA_S0_PERIPHERAL_MAP 0xffc00f6c /* Memory DMA Stream 0 Source Peripheral Map…
437 #define MDMA_D1_IRQ_STATUS 0xffc00fa8 /* Memory DMA Stream 1 Destination Interrupt…
438 … MDMA_D1_PERIPHERAL_MAP 0xffc00fac /* Memory DMA Stream 1 Destination Peripheral Map Register */
450 #define MDMA_S1_IRQ_STATUS 0xffc00fe8 /* Memory DMA Stream 1 Source Interrupt/Stat…
451 #define MDMA_S1_PERIPHERAL_MAP 0xffc00fec /* Memory DMA Stream 1 Source Peripheral Map…
465 #define UART3_IER_SET 0xffc03120 /* Interrupt Enable Register Set */
466 #define UART3_IER_CLEAR 0xffc03124 /* Interrupt Enable Register Clear */
487 /* Port Interrupt 0 Registers (32-bit) */
489 #define PINT0_MASK_SET 0xffc01400 /* Pin Interrupt 0 Mask Set Register */
490 #define PINT0_MASK_CLEAR 0xffc01404 /* Pin Interrupt 0 Mask Clear Register */
491 #define PINT0_REQUEST 0xffc01408 /* Pin Interrupt 0 Interrupt Request Registe…
492 #define PINT0_ASSIGN 0xffc0140c /* Pin Interrupt 0 Port Assign Register */
493 #define PINT0_EDGE_SET 0xffc01410 /* Pin Interrupt 0 Edge-sensitivity Set Regi…
494 #define PINT0_EDGE_CLEAR 0xffc01414 /* Pin Interrupt 0 Edge-sensitivity Clear Re…
495 #define PINT0_INVERT_SET 0xffc01418 /* Pin Interrupt 0 Inversion Set Register */
496 #define PINT0_INVERT_CLEAR 0xffc0141c /* Pin Interrupt 0 Inversion Clear Register …
497 #define PINT0_PINSTATE 0xffc01420 /* Pin Interrupt 0 Pin Status Register */
498 #define PINT0_LATCH 0xffc01424 /* Pin Interrupt 0 Latch Register */
500 /* Port Interrupt 1 Registers (32-bit) */
502 #define PINT1_MASK_SET 0xffc01430 /* Pin Interrupt 1 Mask Set Register */
503 #define PINT1_MASK_CLEAR 0xffc01434 /* Pin Interrupt 1 Mask Clear Register */
504 #define PINT1_REQUEST 0xffc01438 /* Pin Interrupt 1 Interrupt Request Registe…
505 #define PINT1_ASSIGN 0xffc0143c /* Pin Interrupt 1 Port Assign Register */
506 #define PINT1_EDGE_SET 0xffc01440 /* Pin Interrupt 1 Edge-sensitivity Set Regi…
507 #define PINT1_EDGE_CLEAR 0xffc01444 /* Pin Interrupt 1 Edge-sensitivity Clear Re…
508 #define PINT1_INVERT_SET 0xffc01448 /* Pin Interrupt 1 Inversion Set Register */
509 #define PINT1_INVERT_CLEAR 0xffc0144c /* Pin Interrupt 1 Inversion Clear Register …
510 #define PINT1_PINSTATE 0xffc01450 /* Pin Interrupt 1 Pin Status Register */
511 #define PINT1_LATCH 0xffc01454 /* Pin Interrupt 1 Latch Register */
513 /* Port Interrupt 2 Registers (32-bit) */
515 #define PINT2_MASK_SET 0xffc01460 /* Pin Interrupt 2 Mask Set Register */
516 #define PINT2_MASK_CLEAR 0xffc01464 /* Pin Interrupt 2 Mask Clear Register */
517 #define PINT2_REQUEST 0xffc01468 /* Pin Interrupt 2 Interrupt Request Registe…
518 #define PINT2_ASSIGN 0xffc0146c /* Pin Interrupt 2 Port Assign Register */
519 #define PINT2_EDGE_SET 0xffc01470 /* Pin Interrupt 2 Edge-sensitivity Set Regi…
520 #define PINT2_EDGE_CLEAR 0xffc01474 /* Pin Interrupt 2 Edge-sensitivity Clear Re…
521 #define PINT2_INVERT_SET 0xffc01478 /* Pin Interrupt 2 Inversion Set Register */
522 #define PINT2_INVERT_CLEAR 0xffc0147c /* Pin Interrupt 2 Inversion Clear Register …
523 #define PINT2_PINSTATE 0xffc01480 /* Pin Interrupt 2 Pin Status Register */
524 #define PINT2_LATCH 0xffc01484 /* Pin Interrupt 2 Latch Register */
526 /* Port Interrupt 3 Registers (32-bit) */
528 #define PINT3_MASK_SET 0xffc01490 /* Pin Interrupt 3 Mask Set Register */
529 #define PINT3_MASK_CLEAR 0xffc01494 /* Pin Interrupt 3 Mask Clear Register */
530 #define PINT3_REQUEST 0xffc01498 /* Pin Interrupt 3 Interrupt Request Registe…
531 #define PINT3_ASSIGN 0xffc0149c /* Pin Interrupt 3 Port Assign Register */
532 #define PINT3_EDGE_SET 0xffc014a0 /* Pin Interrupt 3 Edge-sensitivity Set Regi…
533 #define PINT3_EDGE_CLEAR 0xffc014a4 /* Pin Interrupt 3 Edge-sensitivity Clear Re…
534 #define PINT3_INVERT_SET 0xffc014a8 /* Pin Interrupt 3 Inversion Set Register */
535 #define PINT3_INVERT_CLEAR 0xffc014ac /* Pin Interrupt 3 Inversion Clear Register …
536 #define PINT3_PINSTATE 0xffc014b0 /* Pin Interrupt 3 Pin Status Register */
537 #define PINT3_LATCH 0xffc014b4 /* Pin Interrupt 3 Latch Register */
706 #define DMA12_IRQ_STATUS 0xffc01c28 /* DMA Channel 12 Interrupt/Status Register …
707 #define DMA12_PERIPHERAL_MAP 0xffc01c2c /* DMA Channel 12 Peripheral Map Register */
722 #define DMA13_IRQ_STATUS 0xffc01c68 /* DMA Channel 13 Interrupt/Status Register …
723 #define DMA13_PERIPHERAL_MAP 0xffc01c6c /* DMA Channel 13 Peripheral Map Register */
738 #define DMA14_IRQ_STATUS 0xffc01ca8 /* DMA Channel 14 Interrupt/Status Register …
739 #define DMA14_PERIPHERAL_MAP 0xffc01cac /* DMA Channel 14 Peripheral Map Register */
754 #define DMA15_IRQ_STATUS 0xffc01ce8 /* DMA Channel 15 Interrupt/Status Register …
755 #define DMA15_PERIPHERAL_MAP 0xffc01cec /* DMA Channel 15 Peripheral Map Register */
770 #define DMA16_IRQ_STATUS 0xffc01d28 /* DMA Channel 16 Interrupt/Status Register …
771 #define DMA16_PERIPHERAL_MAP 0xffc01d2c /* DMA Channel 16 Peripheral Map Register */
786 #define DMA17_IRQ_STATUS 0xffc01d68 /* DMA Channel 17 Interrupt/Status Register …
787 #define DMA17_PERIPHERAL_MAP 0xffc01d6c /* DMA Channel 17 Peripheral Map Register */
802 #define DMA18_IRQ_STATUS 0xffc01da8 /* DMA Channel 18 Interrupt/Status Register …
803 #define DMA18_PERIPHERAL_MAP 0xffc01dac /* DMA Channel 18 Peripheral Map Register */
818 #define DMA19_IRQ_STATUS 0xffc01de8 /* DMA Channel 19 Interrupt/Status Register …
819 #define DMA19_PERIPHERAL_MAP 0xffc01dec /* DMA Channel 19 Peripheral Map Register */
834 #define DMA20_IRQ_STATUS 0xffc01e28 /* DMA Channel 20 Interrupt/Status Register …
835 #define DMA20_PERIPHERAL_MAP 0xffc01e2c /* DMA Channel 20 Peripheral Map Register */
850 #define DMA21_IRQ_STATUS 0xffc01e68 /* DMA Channel 21 Interrupt/Status Register …
851 #define DMA21_PERIPHERAL_MAP 0xffc01e6c /* DMA Channel 21 Peripheral Map Register */
866 #define DMA22_IRQ_STATUS 0xffc01ea8 /* DMA Channel 22 Interrupt/Status Register …
867 #define DMA22_PERIPHERAL_MAP 0xffc01eac /* DMA Channel 22 Peripheral Map Register */
882 #define DMA23_IRQ_STATUS 0xffc01ee8 /* DMA Channel 23 Interrupt/Status Register …
883 #define DMA23_PERIPHERAL_MAP 0xffc01eec /* DMA Channel 23 Peripheral Map Register */
898 #define MDMA_D2_IRQ_STATUS 0xffc01f28 /* Memory DMA Stream 2 Destination Interrupt…
899 … MDMA_D2_PERIPHERAL_MAP 0xffc01f2c /* Memory DMA Stream 2 Destination Peripheral Map Register */
911 #define MDMA_S2_IRQ_STATUS 0xffc01f68 /* Memory DMA Stream 2 Source Interrupt/Stat…
912 #define MDMA_S2_PERIPHERAL_MAP 0xffc01f6c /* Memory DMA Stream 2 Source Peripheral Map…
927 #define MDMA_D3_IRQ_STATUS 0xffc01fa8 /* Memory DMA Stream 3 Destination Interrupt…
928 … MDMA_D3_PERIPHERAL_MAP 0xffc01fac /* Memory DMA Stream 3 Destination Peripheral Map Register */
940 #define MDMA_S3_IRQ_STATUS 0xffc01fe8 /* Memory DMA Stream 3 Source Interrupt/Stat…
941 #define MDMA_S3_PERIPHERAL_MAP 0xffc01fec /* Memory DMA Stream 3 Source Peripheral Map…
955 #define UART1_IER_SET 0xffc02020 /* Interrupt Enable Register Set */
956 #define UART1_IER_CLEAR 0xffc02024 /* Interrupt Enable Register Clear */
960 /* UART2 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-B…
1050 … CAN0_MBTIF1 0xffc02a20 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 …
1051 … CAN0_MBRIF1 0xffc02a24 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 …
1052 #define CAN0_MBIM1 0xffc02a28 /* CAN Controller 0 Mailbox Interrupt Mask R…
1066 … CAN0_MBTIF2 0xffc02a60 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 …
1067 … CAN0_MBRIF2 0xffc02a64 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 …
1068 #define CAN0_MBIM2 0xffc02a68 /* CAN Controller 0 Mailbox Interrupt Mask R…
1072 /* CAN Controller 0 Clock/Interrupt/Counter Registers */
1079 #define CAN0_GIS 0xffc02a94 /* CAN Controller 0 Global Interrupt Status …
1080 #define CAN0_GIM 0xffc02a98 /* CAN Controller 0 Global Interrupt Mask Re…
1081 #define CAN0_GIF 0xffc02a9c /* CAN Controller 0 Global Interrupt Flag Re…
1083 #define CAN0_INTR 0xffc02aa4 /* CAN Controller 0 Interrupt Pending Regist…
1093 … CAN0_AM00L 0xffc02b00 /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
1094 … CAN0_AM00H 0xffc02b04 /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
1095 … CAN0_AM01L 0xffc02b08 /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
1096 … CAN0_AM01H 0xffc02b0c /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
1097 … CAN0_AM02L 0xffc02b10 /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
1098 … CAN0_AM02H 0xffc02b14 /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
1099 … CAN0_AM03L 0xffc02b18 /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
1100 … CAN0_AM03H 0xffc02b1c /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
1101 … CAN0_AM04L 0xffc02b20 /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
1102 … CAN0_AM04H 0xffc02b24 /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
1103 … CAN0_AM05L 0xffc02b28 /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
1104 … CAN0_AM05H 0xffc02b2c /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
1105 … CAN0_AM06L 0xffc02b30 /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
1106 … CAN0_AM06H 0xffc02b34 /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
1107 … CAN0_AM07L 0xffc02b38 /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
1108 … CAN0_AM07H 0xffc02b3c /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
1109 … CAN0_AM08L 0xffc02b40 /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
1110 … CAN0_AM08H 0xffc02b44 /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
1111 … CAN0_AM09L 0xffc02b48 /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
1112 … CAN0_AM09H 0xffc02b4c /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
1113 … CAN0_AM10L 0xffc02b50 /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
1114 … CAN0_AM10H 0xffc02b54 /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
1115 … CAN0_AM11L 0xffc02b58 /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
1116 … CAN0_AM11H 0xffc02b5c /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
1117 … CAN0_AM12L 0xffc02b60 /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
1118 … CAN0_AM12H 0xffc02b64 /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
1119 … CAN0_AM13L 0xffc02b68 /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
1120 … CAN0_AM13H 0xffc02b6c /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
1121 … CAN0_AM14L 0xffc02b70 /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
1122 … CAN0_AM14H 0xffc02b74 /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
1123 … CAN0_AM15L 0xffc02b78 /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
1124 … CAN0_AM15H 0xffc02b7c /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
1128 … CAN0_AM16L 0xffc02b80 /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
1129 … CAN0_AM16H 0xffc02b84 /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
1130 … CAN0_AM17L 0xffc02b88 /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
1131 … CAN0_AM17H 0xffc02b8c /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
1132 … CAN0_AM18L 0xffc02b90 /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
1133 … CAN0_AM18H 0xffc02b94 /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
1134 … CAN0_AM19L 0xffc02b98 /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
1135 … CAN0_AM19H 0xffc02b9c /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
1136 … CAN0_AM20L 0xffc02ba0 /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
1137 … CAN0_AM20H 0xffc02ba4 /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
1138 … CAN0_AM21L 0xffc02ba8 /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
1139 … CAN0_AM21H 0xffc02bac /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
1140 … CAN0_AM22L 0xffc02bb0 /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
1141 … CAN0_AM22H 0xffc02bb4 /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
1142 … CAN0_AM23L 0xffc02bb8 /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
1143 … CAN0_AM23H 0xffc02bbc /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
1144 … CAN0_AM24L 0xffc02bc0 /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
1145 … CAN0_AM24H 0xffc02bc4 /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
1146 … CAN0_AM25L 0xffc02bc8 /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
1147 … CAN0_AM25H 0xffc02bcc /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
1148 … CAN0_AM26L 0xffc02bd0 /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
1149 … CAN0_AM26H 0xffc02bd4 /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
1150 … CAN0_AM27L 0xffc02bd8 /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
1151 … CAN0_AM27H 0xffc02bdc /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
1152 … CAN0_AM28L 0xffc02be0 /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
1153 … CAN0_AM28H 0xffc02be4 /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
1154 … CAN0_AM29L 0xffc02be8 /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
1155 … CAN0_AM29H 0xffc02bec /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
1156 … CAN0_AM30L 0xffc02bf0 /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
1157 … CAN0_AM30H 0xffc02bf4 /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
1158 … CAN0_AM31L 0xffc02bf8 /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
1159 … CAN0_AM31H 0xffc02bfc /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
1433 #define UART3_IER_SET 0xffc03120 /* Interrupt Enable Register Set */
1434 #define UART3_IER_CLEAR 0xffc03124 /* Interrupt Enable Register Clear */
1442 #define NFC_IRQSTAT 0xffc03b08 /* NAND Interrupt Status Register */
1443 #define NFC_IRQMASK 0xffc03b0c /* NAND Interrupt Mask Register */
1460 #define CNT_IMASK 0xffc04204 /* Interrupt Mask Register */
1487 #define OTP_DATA0 0xffc04380 /* OTP/Fuse Data (OTP_DATA0-3) accesses the …
1488 #define OTP_DATA1 0xffc04384 /* OTP/Fuse Data (OTP_DATA0-3) accesses the …
1489 #define OTP_DATA2 0xffc04388 /* OTP/Fuse Data (OTP_DATA0-3) accesses the …
1490 #define OTP_DATA3 0xffc0438c /* OTP/Fuse Data (OTP_DATA0-3) accesses the …
1492 /* Handshake MDMA is not defined in the shared file because it is not available on the ADSP-BF542 p…
1495 /* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
1501 #define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
1502 #define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */
1503 #define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */
1523 #define RTC 0x80 /* Real-Time Clock */
1532 #define PINT0 0x80000 /* Pin Interrupt 0 */
1533 #define PINT1 0x100000 /* Pin Interrupt 1 */
1594 #define SDH_INT_MASK0 0x100 /* SDH Mask 0 */
1595 #define SDH_INT_MASK1 0x200 /* SDH Mask 1 */
1597 #define USB_INT0 0x800 /* USB Interrupt 0 */
1598 #define USB_INT1 0x1000 /* USB Interrupt 1 */
1599 #define USB_INT2 0x2000 /* USB Interrupt 2 */
1610 #define PINT2 0x40000000 /* Pin Interrupt 2 */
1611 #define PINT3 0x80000000 /* Pin Interrupt 3 */
1710 #define TRFC 0x3c000 /* Auto-refresh command period */
1711 #define TRP 0x3c0000 /* Pre charge-to-active command period */
1712 #define TRAS 0x3c00000 /* Min Active-to-pre charge time */
1713 #define TRC 0x3c000000 /* Active-to-active time */
1722 #define TRCD 0xf /* Active-to-Read/write delay */
1729 #define TWTR 0xf0000000 /* Write-to-read delay */
1758 #define PASR 0x7 /* Partial array self-refresh */
1785 #define SRREQ 0x8 /* Self-refresh request */
1786 #define SRACK 0x10 /* Self-refresh acknowledge */
1809 #define ARCENABLE 0x40000 /* DDR Auto-refresh count enable */
1835 #define CRWTACOUNT 0x20000 /* Clear R/W turn-around count */
1836 #define CARCOUNT 0x40000 /* Clear auto-refresh count */
1842 /* Bit masks for (PORTx is PORTA - PORTJ) includes PORTx_FER, PORTx_SET, PORTx_CLEAR, PORTx_DIR_SET…
1861 /* Bit masks for PORTA_MUX - PORTJ_MUX */
1883 #define IB0 0x1 /* Interrupt Bit 0 */
1884 #define IB1 0x2 /* Interrupt Bit 1 */
1885 #define IB2 0x4 /* Interrupt Bit 2 */
1886 #define IB3 0x8 /* Interrupt Bit 3 */
1887 #define IB4 0x10 /* Interrupt Bit 4 */
1888 #define IB5 0x20 /* Interrupt Bit 5 */
1889 #define IB6 0x40 /* Interrupt Bit 6 */
1890 #define IB7 0x80 /* Interrupt Bit 7 */
1891 #define IB8 0x100 /* Interrupt Bit 8 */
1892 #define IB9 0x200 /* Interrupt Bit 9 */
1893 #define IB10 0x400 /* Interrupt Bit 10 */
1894 #define IB11 0x800 /* Interrupt Bit 11 */
1895 #define IB12 0x1000 /* Interrupt Bit 12 */
1896 #define IB13 0x2000 /* Interrupt Bit 13 */
1897 #define IB14 0x4000 /* Interrupt Bit 14 */
1898 #define IB15 0x8000 /* Interrupt Bit 15 */
1905 #define IRQ_ENA 0x10 /* Interrupt Request Enable */
1937 #define TIMIL0 0x1 /* Timer 0 Interrupt */
1938 #define TIMIL1 0x2 /* Timer 1 Interrupt */
1939 #define TIMIL2 0x4 /* Timer 2 Interrupt */
1940 #define TIMIL3 0x8 /* Timer 3 Interrupt */
1949 #define TIMIL4 0x10000 /* Timer 4 Interrupt */
1950 #define TIMIL5 0x20000 /* Timer 5 Interrupt */
1951 #define TIMIL6 0x40000 /* Timer 6 Interrupt */
1952 #define TIMIL7 0x80000 /* Timer 7 Interrupt */
1985 #define NMI 0x4 /* Non Maskable Interrupt */
1993 #define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
2029 #define SIGN_EXT 0x400000 /* Sign Extension or Zero-filled / Data Split Format …
2031 #define SUBSPLT_ODD 0x1000000 /* Sub-split Odd Samples */
2037 #define DLEN_8 (0 << 15) /* 000 - 8 bits */
2038 #define DLEN_10 (1 << 15) /* 001 - 10 bits */
2039 #define DLEN_12 (2 << 15) /* 010 - 12 bits */
2040 #define DLEN_14 (3 << 15) /* 011 - 14 bits */
2041 #define DLEN_16 (4 << 15) /* 100 - 16 bits */
2042 #define DLEN_18 (5 << 15) /* 101 - 18 bits */
2043 #define DLEN_24 (6 << 15) /* 110 - 24 bits */
2066 /* The TWI bit masks fields are from the ADSP-BF538 */
2129 #define XMTINTLEN 0x4 /* Transmit Buffer Interrupt Length */
2130 #define RCVINTLEN 0x8 /* Receive Buffer Interrupt Length */
2139 #define SINITM 0x1 /* Slave Transfer Initiated Interrupt Mask */
2140 #define SCOMPM 0x2 /* Slave Transfer Complete Interrupt Mask */
2141 #define SERRM 0x4 /* Slave Transfer Error Interrupt Mask */
2142 #define SOVFM 0x8 /* Slave Overflow Interrupt Mask */
2143 #define MCOMPM 0x10 /* Master Transfer Complete Interrupt Mask */
2144 #define MERRM 0x20 /* Master Transfer Error Interrupt Mask */
2145 #define XMTSERVM 0x40 /* Transmit FIFO Service Interrupt Mask */
2146 #define RCVSERVM 0x80 /* Receive FIFO Service Interrupt Mask */
2161 #define XMTDATA8 0xff /* Transmit FIFO 8-Bit Data */
2165 #define XMTDATA16 0xffff /* Transmit FIFO 16-Bit Data */
2169 #define RCVDATA8 0xff /* Receive FIFO 8-Bit Data */
2173 #define RCVDATA16 0xffff /* Receive FIFO 16-Bit Data */
2181 #define BCODE_WAKEUP 0x0000 /* boot according to wake-up condition */
2353 #define B0MAP_PAL 0x00000000 /* Map Port A Low to Byte 0 */
2354 #define B0MAP_PBL 0x00000001 /* Map Port B Low to Byte 0 */
2356 #define B1MAP_PAH 0x00000000 /* Map Port A High to Byte 1 */
2357 #define B1MAP_PBH 0x00000100 /* Map Port B High to Byte 1 */
2359 #define B2MAP_PAL 0x00000000 /* Map Port A Low to Byte 2 */
2360 #define B2MAP_PBL 0x00010000 /* Map Port B Low to Byte 2 */
2362 #define B3MAP_PAH 0x00000000 /* Map Port A High to Byte 3 */
2363 #define B3MAP_PBH 0x01000000 /* Map Port B High to Byte 3 */
2367 #define B0MAP_PCL 0x00000000 /* Map Port C Low to Byte 0 */
2368 #define B0MAP_PDL 0x00000001 /* Map Port D Low to Byte 0 */
2369 #define B0MAP_PEL 0x00000002 /* Map Port E Low to Byte 0 */
2370 #define B0MAP_PFL 0x00000003 /* Map Port F Low to Byte 0 */
2371 #define B0MAP_PGL 0x00000004 /* Map Port G Low to Byte 0 */
2372 #define B0MAP_PHL 0x00000005 /* Map Port H Low to Byte 0 */
2373 #define B0MAP_PIL 0x00000006 /* Map Port I Low to Byte 0 */
2374 #define B0MAP_PJL 0x00000007 /* Map Port J Low to Byte 0 */
2376 #define B1MAP_PCH 0x00000000 /* Map Port C High to Byte 1 */
2377 #define B1MAP_PDH 0x00000100 /* Map Port D High to Byte 1 */
2378 #define B1MAP_PEH 0x00000200 /* Map Port E High to Byte 1 */
2379 #define B1MAP_PFH 0x00000300 /* Map Port F High to Byte 1 */
2380 #define B1MAP_PGH 0x00000400 /* Map Port G High to Byte 1 */
2381 #define B1MAP_PHH 0x00000500 /* Map Port H High to Byte 1 */
2382 #define B1MAP_PIH 0x00000600 /* Map Port I High to Byte 1 */
2383 #define B1MAP_PJH 0x00000700 /* Map Port J High to Byte 1 */
2385 #define B2MAP_PCL 0x00000000 /* Map Port C Low to Byte 2 */
2386 #define B2MAP_PDL 0x00010000 /* Map Port D Low to Byte 2 */
2387 #define B2MAP_PEL 0x00020000 /* Map Port E Low to Byte 2 */
2388 #define B2MAP_PFL 0x00030000 /* Map Port F Low to Byte 2 */
2389 #define B2MAP_PGL 0x00040000 /* Map Port G Low to Byte 2 */
2390 #define B2MAP_PHL 0x00050000 /* Map Port H Low to Byte 2 */
2391 #define B2MAP_PIL 0x00060000 /* Map Port I Low to Byte 2 */
2392 #define B2MAP_PJL 0x00070000 /* Map Port J Low to Byte 2 */
2394 #define B3MAP_PCH 0x00000000 /* Map Port C High to Byte 3 */
2395 #define B3MAP_PDH 0x01000000 /* Map Port D High to Byte 3 */
2396 #define B3MAP_PEH 0x02000000 /* Map Port E High to Byte 3 */
2397 #define B3MAP_PFH 0x03000000 /* Map Port F High to Byte 3 */
2398 #define B3MAP_PGH 0x04000000 /* Map Port G High to Byte 3 */
2399 #define B3MAP_PHH 0x05000000 /* Map Port H High to Byte 3 */
2400 #define B3MAP_PIH 0x06000000 /* Map Port I High to Byte 3 */
2401 #define B3MAP_PJH 0x07000000 /* Map Port J High to Byte 3 */