Lines Matching +full:gpio +full:- +full:mux +full:- +full:clock
2 * Copyright 2007-2010 Analog Devices Inc.
4 * Licensed under the ADI BSD license or the GPL-2 (or later)
12 /* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */
23 /* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */
31 /* System Reset and Interrupt Controller (0xFFC00100 - 0xFFC00104) */
102 …rs are not defined in the shared file because they are not available on the ADSP-BF542 processor */
107 #define TWI0_CLKDIV 0xffc00700 /* Clock Divider Register */
124 /* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-…
130 #define SPORT1_TCLKDIV 0xffc00908 /* SPORT1 Transmit Serial Clock Divider Regi…
136 #define SPORT1_RCLKDIV 0xffc00928 /* SPORT1 Receive Serial Clock Divider Regis…
192 #define EBIU_DDRARCT 0xffc00aac /* DDR Auto-refresh Count Register */
479 #define EPPI1_CLKDIV 0xffc0131c /* EPPI1 Clock Divide Register */
487 /* Port Interrupt 0 Registers (32-bit) */
493 #define PINT0_EDGE_SET 0xffc01410 /* Pin Interrupt 0 Edge-sensitivity Set Regi…
494 #define PINT0_EDGE_CLEAR 0xffc01414 /* Pin Interrupt 0 Edge-sensitivity Clear Re…
500 /* Port Interrupt 1 Registers (32-bit) */
506 #define PINT1_EDGE_SET 0xffc01440 /* Pin Interrupt 1 Edge-sensitivity Set Regi…
507 #define PINT1_EDGE_CLEAR 0xffc01444 /* Pin Interrupt 1 Edge-sensitivity Clear Re…
513 /* Port Interrupt 2 Registers (32-bit) */
519 #define PINT2_EDGE_SET 0xffc01470 /* Pin Interrupt 2 Edge-sensitivity Set Regi…
520 #define PINT2_EDGE_CLEAR 0xffc01474 /* Pin Interrupt 2 Edge-sensitivity Clear Re…
526 /* Port Interrupt 3 Registers (32-bit) */
532 #define PINT3_EDGE_SET 0xffc014a0 /* Pin Interrupt 3 Edge-sensitivity Set Regi…
533 #define PINT3_EDGE_CLEAR 0xffc014a4 /* Pin Interrupt 3 Edge-sensitivity Clear Re…
542 #define PORTA 0xffc014c4 /* GPIO Data Register */
543 #define PORTA_SET 0xffc014c8 /* GPIO Data Set Register */
544 #define PORTA_CLEAR 0xffc014cc /* GPIO Data Clear Register */
545 #define PORTA_DIR_SET 0xffc014d0 /* GPIO Direction Set Register */
546 #define PORTA_DIR_CLEAR 0xffc014d4 /* GPIO Direction Clear Register */
547 #define PORTA_INEN 0xffc014d8 /* GPIO Input Enable Register */
553 #define PORTB 0xffc014e4 /* GPIO Data Register */
554 #define PORTB_SET 0xffc014e8 /* GPIO Data Set Register */
555 #define PORTB_CLEAR 0xffc014ec /* GPIO Data Clear Register */
556 #define PORTB_DIR_SET 0xffc014f0 /* GPIO Direction Set Register */
557 #define PORTB_DIR_CLEAR 0xffc014f4 /* GPIO Direction Clear Register */
558 #define PORTB_INEN 0xffc014f8 /* GPIO Input Enable Register */
564 #define PORTC 0xffc01504 /* GPIO Data Register */
565 #define PORTC_SET 0xffc01508 /* GPIO Data Set Register */
566 #define PORTC_CLEAR 0xffc0150c /* GPIO Data Clear Register */
567 #define PORTC_DIR_SET 0xffc01510 /* GPIO Direction Set Register */
568 #define PORTC_DIR_CLEAR 0xffc01514 /* GPIO Direction Clear Register */
569 #define PORTC_INEN 0xffc01518 /* GPIO Input Enable Register */
575 #define PORTD 0xffc01524 /* GPIO Data Register */
576 #define PORTD_SET 0xffc01528 /* GPIO Data Set Register */
577 #define PORTD_CLEAR 0xffc0152c /* GPIO Data Clear Register */
578 #define PORTD_DIR_SET 0xffc01530 /* GPIO Direction Set Register */
579 #define PORTD_DIR_CLEAR 0xffc01534 /* GPIO Direction Clear Register */
580 #define PORTD_INEN 0xffc01538 /* GPIO Input Enable Register */
586 #define PORTE 0xffc01544 /* GPIO Data Register */
587 #define PORTE_SET 0xffc01548 /* GPIO Data Set Register */
588 #define PORTE_CLEAR 0xffc0154c /* GPIO Data Clear Register */
589 #define PORTE_DIR_SET 0xffc01550 /* GPIO Direction Set Register */
590 #define PORTE_DIR_CLEAR 0xffc01554 /* GPIO Direction Clear Register */
591 #define PORTE_INEN 0xffc01558 /* GPIO Input Enable Register */
597 #define PORTF 0xffc01564 /* GPIO Data Register */
598 #define PORTF_SET 0xffc01568 /* GPIO Data Set Register */
599 #define PORTF_CLEAR 0xffc0156c /* GPIO Data Clear Register */
600 #define PORTF_DIR_SET 0xffc01570 /* GPIO Direction Set Register */
601 #define PORTF_DIR_CLEAR 0xffc01574 /* GPIO Direction Clear Register */
602 #define PORTF_INEN 0xffc01578 /* GPIO Input Enable Register */
608 #define PORTG 0xffc01584 /* GPIO Data Register */
609 #define PORTG_SET 0xffc01588 /* GPIO Data Set Register */
610 #define PORTG_CLEAR 0xffc0158c /* GPIO Data Clear Register */
611 #define PORTG_DIR_SET 0xffc01590 /* GPIO Direction Set Register */
612 #define PORTG_DIR_CLEAR 0xffc01594 /* GPIO Direction Clear Register */
613 #define PORTG_INEN 0xffc01598 /* GPIO Input Enable Register */
619 #define PORTH 0xffc015a4 /* GPIO Data Register */
620 #define PORTH_SET 0xffc015a8 /* GPIO Data Set Register */
621 #define PORTH_CLEAR 0xffc015ac /* GPIO Data Clear Register */
622 #define PORTH_DIR_SET 0xffc015b0 /* GPIO Direction Set Register */
623 #define PORTH_DIR_CLEAR 0xffc015b4 /* GPIO Direction Clear Register */
624 #define PORTH_INEN 0xffc015b8 /* GPIO Input Enable Register */
630 #define PORTI 0xffc015c4 /* GPIO Data Register */
631 #define PORTI_SET 0xffc015c8 /* GPIO Data Set Register */
632 #define PORTI_CLEAR 0xffc015cc /* GPIO Data Clear Register */
633 #define PORTI_DIR_SET 0xffc015d0 /* GPIO Direction Set Register */
634 #define PORTI_DIR_CLEAR 0xffc015d4 /* GPIO Direction Clear Register */
635 #define PORTI_INEN 0xffc015d8 /* GPIO Input Enable Register */
641 #define PORTJ 0xffc015e4 /* GPIO Data Register */
642 #define PORTJ_SET 0xffc015e8 /* GPIO Data Set Register */
643 #define PORTJ_CLEAR 0xffc015ec /* GPIO Data Clear Register */
644 #define PORTJ_DIR_SET 0xffc015f0 /* GPIO Direction Set Register */
645 #define PORTJ_DIR_CLEAR 0xffc015f4 /* GPIO Direction Clear Register */
646 #define PORTJ_INEN 0xffc015f8 /* GPIO Input Enable Register */
960 /* UART2 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-B…
977 #define SPORT2_TCLKDIV 0xffc02508 /* SPORT2 Transmit Serial Clock Divider Regi…
983 #define SPORT2_RCLKDIV 0xffc02528 /* SPORT2 Receive Serial Clock Divider Regis…
1002 #define SPORT3_TCLKDIV 0xffc02608 /* SPORT3 Transmit Serial Clock Divider Regi…
1008 #define SPORT3_RCLKDIV 0xffc02628 /* SPORT3 Receive Serial Clock Divider Regis…
1032 #define EPPI2_CLKDIV 0xffc0291c /* EPPI2 Clock Divide Register */
1072 /* CAN Controller 0 Clock/Interrupt/Counter Registers */
1074 #define CAN0_CLOCK 0xffc02a80 /* CAN Controller 0 Clock Register */
1481 /* DMA Peripheral Mux Register */
1487 #define OTP_DATA0 0xffc04380 /* OTP/Fuse Data (OTP_DATA0-3) accesses the …
1488 #define OTP_DATA1 0xffc04384 /* OTP/Fuse Data (OTP_DATA0-3) accesses the …
1489 #define OTP_DATA2 0xffc04388 /* OTP/Fuse Data (OTP_DATA0-3) accesses the …
1490 #define OTP_DATA3 0xffc0438c /* OTP/Fuse Data (OTP_DATA0-3) accesses the …
1492 /* Handshake MDMA is not defined in the shared file because it is not available on the ADSP-BF542 p…
1523 #define RTC 0x80 /* Real-Time Clock */
1697 #define BCLK 0x6 /* Burst clock frequency */
1710 #define TRFC 0x3c000 /* Auto-refresh command period */
1711 #define TRP 0x3c0000 /* Pre charge-to-active command period */
1712 #define TRAS 0x3c00000 /* Min Active-to-pre charge time */
1713 #define TRC 0x3c000000 /* Active-to-active time */
1722 #define TRCD 0xf /* Active-to-Read/write delay */
1729 #define TWTR 0xf0000000 /* Write-to-read delay */
1758 #define PASR 0x7 /* Partial array self-refresh */
1785 #define SRREQ 0x8 /* Self-refresh request */
1786 #define SRACK 0x10 /* Self-refresh acknowledge */
1809 #define ARCENABLE 0x40000 /* DDR Auto-refresh count enable */
1835 #define CRWTACOUNT 0x20000 /* Clear R/W turn-around count */
1836 #define CARCOUNT 0x40000 /* Clear auto-refresh count */
1842 /* Bit masks for (PORTx is PORTA - PORTJ) includes PORTx_FER, PORTx_SET, PORTx_CLEAR, PORTx_DIR_SET…
1844 #define Px0 0x1 /* GPIO 0 */
1845 #define Px1 0x2 /* GPIO 1 */
1846 #define Px2 0x4 /* GPIO 2 */
1847 #define Px3 0x8 /* GPIO 3 */
1848 #define Px4 0x10 /* GPIO 4 */
1849 #define Px5 0x20 /* GPIO 5 */
1850 #define Px6 0x40 /* GPIO 6 */
1851 #define Px7 0x80 /* GPIO 7 */
1852 #define Px8 0x100 /* GPIO 8 */
1853 #define Px9 0x200 /* GPIO 9 */
1854 #define Px10 0x400 /* GPIO 10 */
1855 #define Px11 0x800 /* GPIO 11 */
1856 #define Px12 0x1000 /* GPIO 12 */
1857 #define Px13 0x2000 /* GPIO 13 */
1858 #define Px14 0x4000 /* GPIO 14 */
1859 #define Px15 0x8000 /* GPIO 15 */
1861 /* Bit masks for PORTA_MUX - PORTJ_MUX */
1863 #define PxM0 0x3 /* GPIO Mux 0 */
1864 #define PxM1 0xc /* GPIO Mux 1 */
1865 #define PxM2 0x30 /* GPIO Mux 2 */
1866 #define PxM3 0xc0 /* GPIO Mux 3 */
1867 #define PxM4 0x300 /* GPIO Mux 4 */
1868 #define PxM5 0xc00 /* GPIO Mux 5 */
1869 #define PxM6 0x3000 /* GPIO Mux 6 */
1870 #define PxM7 0xc000 /* GPIO Mux 7 */
1871 #define PxM8 0x30000 /* GPIO Mux 8 */
1872 #define PxM9 0xc0000 /* GPIO Mux 9 */
1873 #define PxM10 0x300000 /* GPIO Mux 10 */
1874 #define PxM11 0xc00000 /* GPIO Mux 11 */
1875 #define PxM12 0x3000000 /* GPIO Mux 12 */
1876 #define PxM13 0xc000000 /* GPIO Mux 13 */
1877 #define PxM14 0x30000000 /* GPIO Mux 14 */
1878 #define PxM15 0xc0000000 /* GPIO Mux 15 */
1908 #define CLK_SEL 0x80 /* Timer Clock Select */
1993 #define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
2020 #define ICLKGEN 0x200 /* Internal Clock Generation */
2029 #define SIGN_EXT 0x400000 /* Sign Extension or Zero-filled / Data Split Format …
2031 #define SUBSPLT_ODD 0x1000000 /* Sub-split Odd Samples */
2037 #define DLEN_8 (0 << 15) /* 000 - 8 bits */
2038 #define DLEN_10 (1 << 15) /* 001 - 10 bits */
2039 #define DLEN_12 (2 << 15) /* 010 - 12 bits */
2040 #define DLEN_14 (3 << 15) /* 011 - 14 bits */
2041 #define DLEN_16 (4 << 15) /* 100 - 16 bits */
2042 #define DLEN_18 (5 << 15) /* 101 - 18 bits */
2043 #define DLEN_24 (6 << 15) /* 110 - 24 bits */
2066 /* The TWI bit masks fields are from the ADSP-BF538 */
2079 #define CLKLOW 0xff /* Clock Low */
2080 #define CLKHI 0xff00 /* Clock High */
2107 #define SCLOVR 0x8000 /* Serial Clock Override */
2122 #define SCLSEN 0x80 /* Serial Clock Sense */
2161 #define XMTDATA8 0xff /* Transmit FIFO 8-Bit Data */
2165 #define XMTDATA16 0xffff /* Transmit FIFO 16-Bit Data */
2169 #define RCVDATA8 0xff /* Receive FIFO 8-Bit Data */
2173 #define RCVDATA16 0xffff /* Receive FIFO 16-Bit Data */
2181 #define BCODE_WAKEUP 0x0000 /* boot according to wake-up condition */
2332 #define MUX(b15,b14,b13,b12,b11,b10,b9,b8,b7,b6,b5,b4,b3,b2,b1,b0) \ macro