Lines Matching +full:multi +full:- +full:line
2 * Copyright 2008-2010 Analog Devices Inc.
4 * Licensed under the ADI BSD license or the GPL-2 (or later)
10 /* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
13 /* The following are the #defines needed by ADSP-BF547 that are not in the common header */
50 #define SPORT0_MCMC1 0xffc00838 /* SPORT0 Multi channel Configuration Regist…
51 #define SPORT0_MCMC2 0xffc0083c /* SPORT0 Multi channel Configuration Regist…
52 #define SPORT0_MTCS0 0xffc00840 /* SPORT0 Multi channel Transmit Select Regi…
53 #define SPORT0_MTCS1 0xffc00844 /* SPORT0 Multi channel Transmit Select Regi…
54 #define SPORT0_MTCS2 0xffc00848 /* SPORT0 Multi channel Transmit Select Regi…
55 #define SPORT0_MTCS3 0xffc0084c /* SPORT0 Multi channel Transmit Select Regi…
56 #define SPORT0_MRCS0 0xffc00850 /* SPORT0 Multi channel Receive Select Regis…
57 #define SPORT0_MRCS1 0xffc00854 /* SPORT0 Multi channel Receive Select Regis…
58 #define SPORT0_MRCS2 0xffc00858 /* SPORT0 Multi channel Receive Select Regis…
59 #define SPORT0_MRCS3 0xffc0085c /* SPORT0 Multi channel Receive Select Regis…
69 #define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */
72 … 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
73 …P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
83 #define UART2_LCR 0xffc0210c /* Line Control Register */
85 #define UART2_LSR 0xffc02114 /* Line Status Register */
133 #define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */
143 #define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */
144 #define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */
145 #define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */
146 #define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */
147 #define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */
148 #define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */
149 #define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */
242 #define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side dela…
244 #define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */
245 #define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */
246 #define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */
255 #define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration o…
372 #define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destinatio…
373 #define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destinatio…
374 #define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transf…
375 #define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transf…
380 #define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destinatio…
381 #define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destinatio…
382 #define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transf…
383 #define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transf…
388 #define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destinatio…
389 #define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destinatio…
390 #define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transf…
391 #define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transf…
396 #define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destinatio…
397 #define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destinatio…
398 #define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transf…
399 #define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transf…
404 #define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destinatio…
405 #define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destinatio…
406 #define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transf…
407 #define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transf…
412 #define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destinatio…
413 #define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destinatio…
414 #define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transf…
415 #define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transf…
420 #define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destinatio…
421 #define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destinatio…
422 #define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transf…
423 #define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transf…
428 #define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destinatio…
429 #define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destinatio…
430 #define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transf…
431 #define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transf…
445 #define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of th…
487 /* and MULTI BIT READ MACROS */
580 #define RY_TRANS 0xff /* Transparent Color - R/Y Component */
581 #define GU_TRANS 0xff00 /* Transparent Color - G/U Component */
582 #define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */
648 #define MULTI_START 0x2 /* Start Multi-DMA Op */
649 #define ULTRA_START 0x4 /* Start Ultra-DMA Op */
657 #define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
658 #define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
663 #define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
675 #define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
676 #define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
677 #define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
679 #define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask…
680 #define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt m…
681 #define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt …
687 #define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
688 #define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
689 #define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
691 #define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt stat…
692 #define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt s…
693 #define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt …
697 #define ATAPI_INTR 0x1 /* Device interrupt to host line status */
698 #define ATAPI_DASP 0x2 /* Device dasp to host line status */
699 #define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
700 #define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
701 #define ATAPI_ADDR 0x70 /* ATAPI address line status */
702 #define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
703 #define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
704 #define ATAPI_DIOWN 0x200 /* ATAPI write line status */
705 #define ATAPI_DIORN 0x400 /* ATAPI read line status */
706 #define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
712 #define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */
713 #define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */
757 #define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */
907 #define LSDEV 0x20 /* Low-speed indicator */
908 #define FSDEV 0x40 /* Full or High-speed indicator */
1053 #define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address…
1057 #define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address…
1061 #define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DM…
1065 #define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DM…