Lines Matching full:for
10 /* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
195 #define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx …
196 #define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to …
197 #define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */
198 #define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */
199 #define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interru…
200 #define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */
202 #define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed …
205 #define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */
209 #define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint …
210 … USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register fo…
211 … USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register fo…
212 #define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint …
213 #define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpo…
216 …ffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoin…
217 …3c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
218 …3c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
219 …ffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoin…
220 #define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt a…
243 #define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBU…
244 #define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */
245 #define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */
246 #define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */
248 /* (APHY_CNTRL is for ADI usage only) */
252 /* (APHY_CALIB is for ADI usage only) */
257 /* (PHY_TEST is for ADI usage only) */
259 #define USB_PHY_TEST 0xffc03dec /* Used for reducing simulation time and sim…
260 #define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for …
261 #define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for th…
265 #define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0…
266 #define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */
267 #define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0…
268 #define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpo…
270 …ffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoin…
272 …ffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoin…
273 …20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout …
278 #define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1…
279 #define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */
280 #define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1…
281 #define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpo…
283 …ffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoin…
285 …ffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoin…
286 …60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout …
291 #define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2…
292 #define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */
293 #define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2…
294 #define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpo…
296 …ffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoin…
298 …ffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoin…
299 …a0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout …
304 #define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3…
305 #define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */
306 #define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3…
307 #define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpo…
309 …ffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoin…
311 …ffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoin…
312 …e0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout …
317 #define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4…
318 #define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */
319 #define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4…
320 #define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpo…
322 …ffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoin…
324 …ffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoin…
325 …20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout …
330 #define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5…
331 #define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */
332 #define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5…
333 #define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpo…
335 …ffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoin…
337 …ffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoin…
338 …60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout …
343 #define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6…
344 #define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */
345 #define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6…
346 #define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpo…
348 …ffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoin…
350 …ffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoin…
351 …a0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout …
356 #define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7…
357 #define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */
358 #define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7…
359 #define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpo…
361 …ffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoin…
363 …ffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoin…
364 …e0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout …
367 #define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA …
372 …DDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel …
373 …DRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel …
374 …_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel …
375 …DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel …
380 …DDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel …
381 …DRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel …
382 …_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel …
383 …DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel …
388 …DDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel …
389 …DRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel …
390 …_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel …
391 …DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel …
396 …DDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel …
397 …DRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel …
398 …_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel …
399 …DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel …
404 …DDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel …
405 …DRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel …
406 …_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel …
407 …DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel …
412 …DDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel …
413 …DRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel …
414 …_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel …
415 …DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel …
420 …DDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel …
421 …DRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel …
422 …_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel …
423 …DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel …
428 …DDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel …
429 …DRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel …
430 …_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel …
431 …DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel …
436 #define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the …
437 #define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad inter…
440 …AD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed …
461 #define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversio…
490 /* Bit masks for PIXC_CTL */
504 /* Bit masks for PIXC_AHSTART */
508 /* Bit masks for PIXC_AHEND */
512 /* Bit masks for PIXC_AVSTART */
516 /* Bit masks for PIXC_AVEND */
520 /* Bit masks for PIXC_ATRANSP */
524 /* Bit masks for PIXC_BHSTART */
528 /* Bit masks for PIXC_BHEND */
532 /* Bit masks for PIXC_BVSTART */
536 /* Bit masks for PIXC_BVEND */
540 /* Bit masks for PIXC_BTRANSP */
544 /* Bit masks for PIXC_INTRSTAT */
551 /* Bit masks for PIXC_RYCON */
558 /* Bit masks for PIXC_GUCON */
565 /* Bit masks for PIXC_BVCON */
572 /* Bit masks for PIXC_CCBIAS */
578 /* Bit masks for PIXC_TC */
584 /* Bit masks for HOST_CONTROL */
597 /* Bit masks for HOST_STATUS */
610 /* Bit masks for HOST_TIMEOUT */
614 /* Bit masks for KPAD_CTL */
621 /* Bit masks for KPAD_PRESCALE */
625 /* Bit masks for KPAD_MSEL */
630 /* Bit masks for KPAD_ROWCOL */
635 /* Bit masks for KPAD_STAT */
641 /* Bit masks for KPAD_SOFTEVAL */
645 /* Bit masks for ATAPI_CONTROL */
660 /* Bit masks for ATAPI_STATUS */
667 /* Bit masks for ATAPI_DEV_ADDR */
671 /* Bit masks for ATAPI_INT_MASK */
683 /* Bit masks for ATAPI_INT_STATUS */
695 /* Bit masks for ATAPI_LINE_STATUS */
708 /* Bit masks for ATAPI_SM_STATE */
715 /* Bit masks for ATAPI_TERMINATE */
719 /* Bit masks for ATAPI_REG_TIM_0 */
721 #define T2_REG 0xff /* End of cycle time for register access transfers */
724 /* Bit masks for ATAPI_PIO_TIM_0 */
730 /* Bit masks for ATAPI_PIO_TIM_1 */
732 #define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */
734 /* Bit masks for ATAPI_MULTI_TIM_0 */
739 /* Bit masks for ATAPI_MULTI_TIM_1 */
744 /* Bit masks for ATAPI_MULTI_TIM_2 */
747 #define TEOC 0xff00 /* Selects end of cycle for DMA */
749 /* Bit masks for ATAPI_ULTRA_TIM_0 */
751 #define TACK 0xff /* Selects setup and hold times for TACK */
754 /* Bit masks for ATAPI_ULTRA_TIM_1 */
759 /* Bit masks for ATAPI_ULTRA_TIM_2 */
764 /* Bit masks for ATAPI_ULTRA_TIM_3 */
766 #define TZAH 0xff /* Selects minimum delay required for output */
769 /* Bit masks for TIMER_ENABLE1 */
775 /* Bit masks for TIMER_DISABLE1 */
781 /* Bit masks for TIMER_STATUS1 */
793 /* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
795 /* Bit masks for USB_FADDR */
799 /* Bit masks for USB_POWER */
810 /* Bit masks for USB_INTRTX */
821 /* Bit masks for USB_INTRRX */
831 /* Bit masks for USB_INTRTXE */
842 /* Bit masks for USB_INTRRXE */
852 /* Bit masks for USB_INTRUSB */
863 /* Bit masks for USB_INTRUSBE */
874 /* Bit masks for USB_FRAME */
878 /* Bit masks for USB_INDEX */
882 /* Bit masks for USB_GLOBAL_CTL */
900 /* Bit masks for USB_OTG_DEV_CTL */
911 /* Bit masks for USB_OTG_VBUS_IRQ */
915 #define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging V…
916 #define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBU…
920 /* Bit masks for USB_OTG_VBUS_MASK */
929 /* Bit masks for USB_CSR0 */
947 /* Bit masks for USB_COUNT0 */
951 /* Bit masks for USB_NAKLIMIT0 */
955 /* Bit masks for USB_TX_MAX_PACKET */
959 /* Bit masks for USB_RX_MAX_PACKET */
963 /* Bit masks for USB_TXCSR */
967 #define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
975 #define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
982 /* Bit masks for USB_TXCOUNT */
986 /* Bit masks for USB_RXCSR */
990 #define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
999 #define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
1002 #define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
1009 /* Bit masks for USB_RXCOUNT */
1013 /* Bit masks for USB_TXTYPE */
1018 /* Bit masks for USB_TXINTERVAL */
1020 #define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
1022 /* Bit masks for USB_RXTYPE */
1027 /* Bit masks for USB_RXINTERVAL */
1029 #define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
1031 /* Bit masks for USB_DMA_INTERRUPT */
1042 /* Bit masks for USB_DMAxCONTROL */
1051 /* Bit masks for USB_DMAxADDRHIGH */
1053 …DDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master chan…
1055 /* Bit masks for USB_DMAxADDRLOW */
1057 …ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master chan…
1059 /* Bit masks for USB_DMAxCOUNTHIGH */
1061 #define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DM…
1063 /* Bit masks for USB_DMAxCOUNTLOW */
1065 #define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DM…