Lines Matching +full:multi +full:- +full:line

2  * Copyright 2007-2010 Analog Devices Inc.
4 * Licensed under the ADI BSD license or the GPL-2 (or later)
10 /* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
13 /* The following are the #defines needed by ADSP-BF542 that are not in the common header */
25 #define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */
35 #define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */
36 #define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */
37 #define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */
38 #define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */
39 #define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */
40 #define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */
41 #define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */
128 #define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side dela…
130 #define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */
131 #define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */
132 #define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */
141 #define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration o…
257 #define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destinatio…
258 #define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destinatio…
259 #define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transf…
260 #define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transf…
265 #define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destinatio…
266 #define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destinatio…
267 #define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transf…
268 #define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transf…
273 #define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destinatio…
274 #define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destinatio…
275 #define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transf…
276 #define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transf…
281 #define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destinatio…
282 #define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destinatio…
283 #define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transf…
284 #define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transf…
289 #define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destinatio…
290 #define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destinatio…
291 #define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transf…
292 #define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transf…
297 #define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destinatio…
298 #define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destinatio…
299 #define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transf…
300 #define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transf…
305 #define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destinatio…
306 #define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destinatio…
307 #define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transf…
308 #define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transf…
313 #define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destinatio…
314 #define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destinatio…
315 #define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transf…
316 #define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transf…
330 /* and MULTI BIT READ MACROS */
367 #define MULTI_START 0x2 /* Start Multi-DMA Op */
368 #define ULTRA_START 0x4 /* Start Ultra-DMA Op */
376 #define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
377 #define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
382 #define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
394 #define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
395 #define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
396 #define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
398 #define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask…
399 #define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt m…
400 #define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt …
406 #define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
407 #define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
408 #define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
410 #define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt stat…
411 #define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt s…
412 #define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt …
416 #define ATAPI_INTR 0x1 /* Device interrupt to host line status */
417 #define ATAPI_DASP 0x2 /* Device dasp to host line status */
418 #define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
419 #define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
420 #define ATAPI_ADDR 0x70 /* ATAPI address line status */
421 #define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
422 #define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
423 #define ATAPI_DIOWN 0x200 /* ATAPI write line status */
424 #define ATAPI_DIORN 0x400 /* ATAPI read line status */
425 #define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
431 #define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */
432 #define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */
476 #define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */
600 #define LSDEV 0x20 /* Low-speed indicator */
601 #define FSDEV 0x40 /* Full or High-speed indicator */
746 #define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address…
750 #define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address…
754 #define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DM…
758 #define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DM…
762 /* MULTI BIT MACRO ENUMERATIONS */