Lines Matching full:for
10 /* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
81 #define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx …
82 #define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to …
83 #define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */
84 #define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */
85 #define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interru…
86 #define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */
88 #define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed …
91 #define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */
95 #define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint …
96 … USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register fo…
97 … USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register fo…
98 #define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint …
99 #define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpo…
102 …ffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoin…
103 …3c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
104 …3c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
105 …ffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoin…
106 #define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt a…
129 #define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBU…
130 #define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */
131 #define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */
132 #define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */
134 /* (APHY_CNTRL is for ADI usage only) */
138 /* (APHY_CALIB is for ADI usage only) */
143 /* (PHY_TEST is for ADI usage only) */
145 #define USB_PHY_TEST 0xffc03dec /* Used for reducing simulation time and sim…
146 #define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for …
147 #define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for th…
151 #define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0…
152 #define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */
153 #define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0…
154 #define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpo…
156 …ffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoin…
158 …ffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoin…
159 …20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout …
164 #define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1…
165 #define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */
166 #define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1…
167 #define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpo…
169 …ffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoin…
171 …ffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoin…
172 …60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout …
177 #define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2…
178 #define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */
179 #define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2…
180 #define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpo…
182 …ffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoin…
184 …ffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoin…
185 …a0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout …
190 #define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3…
191 #define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */
192 #define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3…
193 #define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpo…
195 …ffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoin…
197 …ffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoin…
198 …e0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout …
203 #define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4…
204 #define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */
205 #define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4…
206 #define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpo…
208 …ffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoin…
210 …ffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoin…
211 …20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout …
216 #define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5…
217 #define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */
218 #define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5…
219 #define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpo…
221 …ffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoin…
223 …ffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoin…
224 …60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout …
229 #define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6…
230 #define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */
231 #define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6…
232 #define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpo…
234 …ffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoin…
236 …ffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoin…
237 …a0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout …
242 #define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7…
243 #define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */
244 #define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7…
245 #define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpo…
247 …ffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoin…
249 …ffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoin…
250 …f0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout …
252 #define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA …
257 …DDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel …
258 …DRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel …
259 …_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel …
260 …DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel …
265 …DDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel …
266 …DRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel …
267 …_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel …
268 …DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel …
273 …DDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel …
274 …DRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel …
275 …_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel …
276 …DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel …
281 …DDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel …
282 …DRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel …
283 …_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel …
284 …DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel …
289 …DDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel …
290 …DRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel …
291 …_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel …
292 …DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel …
297 …DDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel …
298 …DRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel …
299 …_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel …
300 …DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel …
305 …DDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel …
306 …DRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel …
307 …_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel …
308 …DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel …
313 …DDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel …
314 …DRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel …
315 …_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel …
316 …DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel …
321 #define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the …
322 #define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad inter…
325 …AD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed …
333 /* Bit masks for KPAD_CTL */
340 /* Bit masks for KPAD_PRESCALE */
344 /* Bit masks for KPAD_MSEL */
349 /* Bit masks for KPAD_ROWCOL */
354 /* Bit masks for KPAD_STAT */
360 /* Bit masks for KPAD_SOFTEVAL */
364 /* Bit masks for ATAPI_CONTROL */
379 /* Bit masks for ATAPI_STATUS */
386 /* Bit masks for ATAPI_DEV_ADDR */
390 /* Bit masks for ATAPI_INT_MASK */
402 /* Bit masks for ATAPI_INT_STATUS */
414 /* Bit masks for ATAPI_LINE_STATUS */
427 /* Bit masks for ATAPI_SM_STATE */
434 /* Bit masks for ATAPI_TERMINATE */
438 /* Bit masks for ATAPI_REG_TIM_0 */
440 #define T2_REG 0xff /* End of cycle time for register access transfers */
443 /* Bit masks for ATAPI_PIO_TIM_0 */
449 /* Bit masks for ATAPI_PIO_TIM_1 */
451 #define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */
453 /* Bit masks for ATAPI_MULTI_TIM_0 */
458 /* Bit masks for ATAPI_MULTI_TIM_1 */
463 /* Bit masks for ATAPI_MULTI_TIM_2 */
466 #define TEOC 0xff00 /* Selects end of cycle for DMA */
468 /* Bit masks for ATAPI_ULTRA_TIM_0 */
470 #define TACK 0xff /* Selects setup and hold times for TACK */
473 /* Bit masks for ATAPI_ULTRA_TIM_1 */
478 /* Bit masks for ATAPI_ULTRA_TIM_2 */
483 /* Bit masks for ATAPI_ULTRA_TIM_3 */
485 #define TZAH 0xff /* Selects minimum delay required for output */
488 /* Bit masks for USB_FADDR */
492 /* Bit masks for USB_POWER */
503 /* Bit masks for USB_INTRTX */
514 /* Bit masks for USB_INTRRX */
524 /* Bit masks for USB_INTRTXE */
535 /* Bit masks for USB_INTRRXE */
545 /* Bit masks for USB_INTRUSB */
556 /* Bit masks for USB_INTRUSBE */
567 /* Bit masks for USB_FRAME */
571 /* Bit masks for USB_INDEX */
575 /* Bit masks for USB_GLOBAL_CTL */
593 /* Bit masks for USB_OTG_DEV_CTL */
604 /* Bit masks for USB_OTG_VBUS_IRQ */
608 #define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging V…
609 #define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBU…
613 /* Bit masks for USB_OTG_VBUS_MASK */
622 /* Bit masks for USB_CSR0 */
640 /* Bit masks for USB_COUNT0 */
644 /* Bit masks for USB_NAKLIMIT0 */
648 /* Bit masks for USB_TX_MAX_PACKET */
652 /* Bit masks for USB_RX_MAX_PACKET */
656 /* Bit masks for USB_TXCSR */
660 #define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
668 #define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
675 /* Bit masks for USB_TXCOUNT */
679 /* Bit masks for USB_RXCSR */
683 #define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
692 #define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
695 #define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
702 /* Bit masks for USB_RXCOUNT */
706 /* Bit masks for USB_TXTYPE */
711 /* Bit masks for USB_TXINTERVAL */
713 #define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
715 /* Bit masks for USB_RXTYPE */
720 /* Bit masks for USB_RXINTERVAL */
722 #define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
724 /* Bit masks for USB_DMA_INTERRUPT */
735 /* Bit masks for USB_DMAxCONTROL */
744 /* Bit masks for USB_DMAxADDRHIGH */
746 …DDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master chan…
748 /* Bit masks for USB_DMAxADDRLOW */
750 …ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master chan…
752 /* Bit masks for USB_DMAxCOUNTHIGH */
754 #define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DM…
756 /* Bit masks for USB_DMAxCOUNTLOW */
758 #define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DM…