Lines Matching +full:interrupt +full:- +full:map +full:- +full:mask
2 * Copyright 2008-2010 Analog Devices Inc.
4 * Licensed under the ADI BSD license or the GPL-2 (or later)
10 /* Clock/Regulator Control (0xFFC00000 - 0xFFC000FF) */
11 #define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */
12 #define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */
13 #define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
14 #define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */
15 #define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
23 /* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
24 #define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */
27 #define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */
28 #define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
29 #define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
30 #define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
31 #define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
32 #define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */
33 #define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */
34 #define SIC_IMASK1 0xFFC00128 /* Interrupt Mask Register 1 */
35 #define SIC_ISR1 0xFFC0012C /* Interrupt Status Register 1 */
36 #define SIC_IWR1 0xFFC00130 /* Interrupt Wakeup Register 1 */
37 #define SIC_IAR4 0xFFC00134 /* Interrupt Assignment Register 4 */
38 #define SIC_IAR5 0xFFC00138 /* Interrupt Assignment Register 5 */
39 #define SIC_IAR6 0xFFC0013C /* Interrupt Assignment Register 6 */
42 /* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
48 /* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
50 #define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
51 #define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
58 /* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
61 #define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
62 #define UART0_IER 0xFFC00404 /* Interrupt Enable Register */
63 #define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
64 #define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */
72 /* SPI0 Controller (0xFFC00500 - 0xFFC005FF) */
84 /* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */
105 /* Programmable Flags (0xFFC00700 - 0xFFC007FF) */
106 #define FIO_FLAG_D 0xFFC00700 /* Flag Mask to directly specify state of pins */
107 #define FIO_FLAG_C 0xFFC00704 /* Peripheral Interrupt Flag Register (clear) */
108 #define FIO_FLAG_S 0xFFC00708 /* Peripheral Interrupt Flag Register (set) */
109 #define FIO_FLAG_T 0xFFC0070C /* Flag Mask to directly toggle state of pins */
110 #define FIO_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Register (set directly) */
111 #define FIO_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Register (clear) */
112 #define FIO_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Register (set) */
113 #define FIO_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Register (toggle) */
114 #define FIO_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Register (set directly) */
115 #define FIO_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Register (clear) */
116 #define FIO_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Register (set) */
117 #define FIO_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Register (toggle) */
125 /* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
138 #define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
139 #define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
140 #define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
141 #define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
142 #define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
143 #define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
144 #define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
145 #define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
146 #define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
147 #define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
150 /* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
163 #define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
164 #define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
165 #define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
166 #define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
167 #define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
168 #define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
169 #define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
170 #define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
171 #define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
172 #define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
175 /* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
189 /* DMA Controller 0 Traffic Control Registers (0xFFC00B00 - 0xFFC00BFF) */
196 /* DMA Controller 0 (0xFFC00C00 - 0xFFC00FFF) */
207 #define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
208 #define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
221 #define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
222 #define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
235 #define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
236 #define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
249 #define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
250 #define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
263 #define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
264 #define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
277 #define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
278 #define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
291 #define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
292 #define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
305 #define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
306 #define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
319 #define MDMA_D0_IRQ_STATUS 0xFFC00E28 /* MemDMA0 Stream 0 Destination Interrupt/Status Register */
320 #define MDMA_D0_PERIPHERAL_MAP 0xFFC00E2C /* MemDMA0 Stream 0 Destination Peripheral Map Register */
333 #define MDMA_S0_IRQ_STATUS 0xFFC00E68 /* MemDMA0 Stream 0 Source Interrupt/Status Register */
334 #define MDMA_S0_PERIPHERAL_MAP 0xFFC00E6C /* MemDMA0 Stream 0 Source Peripheral Map Register */
347 #define MDMA_D1_IRQ_STATUS 0xFFC00EA8 /* MemDMA0 Stream 1 Destination Interrupt/Status Register */
348 #define MDMA_D1_PERIPHERAL_MAP 0xFFC00EAC /* MemDMA0 Stream 1 Destination Peripheral Map Register */
361 #define MDMA_S1_IRQ_STATUS 0xFFC00EE8 /* MemDMA0 Stream 1 Source Interrupt/Status Register */
362 #define MDMA_S1_PERIPHERAL_MAP 0xFFC00EEC /* MemDMA0 Stream 1 Source Peripheral Map Register */
367 /* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */
375 /* Two-Wire Interface 0 (0xFFC01400 - 0xFFC014FF) */
384 #define TWI0_INT_STAT 0xFFC01420 /* TWI0 Master Interrupt Register */
385 #define TWI0_INT_MASK 0xFFC01424 /* TWI0 Master Interrupt Mask Register */
401 /* General-Purpose Ports (0xFFC01500 - 0xFFC015FF) */
430 /* DMA Controller 1 Traffic Control Registers (0xFFC01B00 - 0xFFC01BFF) */
437 /* DMA Controller 1 (0xFFC01C00 - 0xFFC01FFF) */
447 #define DMA8_IRQ_STATUS 0xFFC01C28 /* DMA Channel 8 Interrupt/Status Register */
448 #define DMA8_PERIPHERAL_MAP 0xFFC01C2C /* DMA Channel 8 Peripheral Map Register */
461 #define DMA9_IRQ_STATUS 0xFFC01C68 /* DMA Channel 9 Interrupt/Status Register */
462 #define DMA9_PERIPHERAL_MAP 0xFFC01C6C /* DMA Channel 9 Peripheral Map Register */
475 #define DMA10_IRQ_STATUS 0xFFC01CA8 /* DMA Channel 10 Interrupt/Status Register */
476 #define DMA10_PERIPHERAL_MAP 0xFFC01CAC /* DMA Channel 10 Peripheral Map Register */
489 #define DMA11_IRQ_STATUS 0xFFC01CE8 /* DMA Channel 11 Interrupt/Status Register */
490 #define DMA11_PERIPHERAL_MAP 0xFFC01CEC /* DMA Channel 11 Peripheral Map Register */
503 #define DMA12_IRQ_STATUS 0xFFC01D28 /* DMA Channel 12 Interrupt/Status Register */
504 #define DMA12_PERIPHERAL_MAP 0xFFC01D2C /* DMA Channel 12 Peripheral Map Register */
517 #define DMA13_IRQ_STATUS 0xFFC01D68 /* DMA Channel 13 Interrupt/Status Register */
518 #define DMA13_PERIPHERAL_MAP 0xFFC01D6C /* DMA Channel 13 Peripheral Map Register */
531 #define DMA14_IRQ_STATUS 0xFFC01DA8 /* DMA Channel 14 Interrupt/Status Register */
532 #define DMA14_PERIPHERAL_MAP 0xFFC01DAC /* DMA Channel 14 Peripheral Map Register */
545 #define DMA15_IRQ_STATUS 0xFFC01DE8 /* DMA Channel 15 Interrupt/Status Register */
546 #define DMA15_PERIPHERAL_MAP 0xFFC01DEC /* DMA Channel 15 Peripheral Map Register */
559 #define DMA16_IRQ_STATUS 0xFFC01E28 /* DMA Channel 16 Interrupt/Status Register */
560 #define DMA16_PERIPHERAL_MAP 0xFFC01E2C /* DMA Channel 16 Peripheral Map Register */
573 #define DMA17_IRQ_STATUS 0xFFC01E68 /* DMA Channel 17 Interrupt/Status Register */
574 #define DMA17_PERIPHERAL_MAP 0xFFC01E6C /* DMA Channel 17 Peripheral Map Register */
587 #define DMA18_IRQ_STATUS 0xFFC01EA8 /* DMA Channel 18 Interrupt/Status Register */
588 #define DMA18_PERIPHERAL_MAP 0xFFC01EAC /* DMA Channel 18 Peripheral Map Register */
601 #define DMA19_IRQ_STATUS 0xFFC01EE8 /* DMA Channel 19 Interrupt/Status Register */
602 #define DMA19_PERIPHERAL_MAP 0xFFC01EEC /* DMA Channel 19 Peripheral Map Register */
615 #define MDMA_D2_IRQ_STATUS 0xFFC01F28 /* MemDMA1 Stream 0 Destination Interrupt/Status Register */
616 #define MDMA_D2_PERIPHERAL_MAP 0xFFC01F2C /* MemDMA1 Stream 0 Destination Peripheral Map Register */
629 #define MDMA_S2_IRQ_STATUS 0xFFC01F68 /* MemDMA1 Stream 0 Source Interrupt/Status Register */
630 #define MDMA_S2_PERIPHERAL_MAP 0xFFC01F6C /* MemDMA1 Stream 0 Source Peripheral Map Register */
643 #define MDMA_D3_IRQ_STATUS 0xFFC01FA8 /* MemDMA1 Stream 1 Destination Interrupt/Status Register */
644 #define MDMA_D3_PERIPHERAL_MAP 0xFFC01FAC /* MemDMA1 Stream 1 Destination Peripheral Map Register */
657 #define MDMA_S3_IRQ_STATUS 0xFFC01FE8 /* MemDMA1 Stream 1 Source Interrupt/Status Register */
658 #define MDMA_S3_PERIPHERAL_MAP 0xFFC01FEC /* MemDMA1 Stream 1 Source Peripheral Map Register */
663 /* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
666 #define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
667 #define UART1_IER 0xFFC02004 /* Interrupt Enable Register */
668 #define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
669 #define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */
677 /* UART2 Controller (0xFFC02100 - 0xFFC021FF) */
680 #define UART2_DLL 0xFFC02100 /* Divisor Latch (Low-Byte) */
681 #define UART2_IER 0xFFC02104 /* Interrupt Enable Register */
682 #define UART2_DLH 0xFFC02104 /* Divisor Latch (High-Byte) */
683 #define UART2_IIR 0xFFC02108 /* Interrupt Identification Register */
691 /* Two-Wire Interface 1 (0xFFC02200 - 0xFFC022FF) */
700 #define TWI1_INT_STAT 0xFFC02220 /* TWI1 Master Interrupt Register */
701 #define TWI1_INT_MASK 0xFFC02224 /* TWI1 Master Interrupt Mask Register */
717 /* SPI1 Controller (0xFFC02300 - 0xFFC023FF) */
727 /* SPI2 Controller (0xFFC02400 - 0xFFC024FF) */
737 /* SPORT2 Controller (0xFFC02500 - 0xFFC025FF) */
750 #define SPORT2_MCMC1 0xFFC02538 /* SPORT2 Multi-Channel Configuration Register 1 */
751 #define SPORT2_MCMC2 0xFFC0253C /* SPORT2 Multi-Channel Configuration Register 2 */
752 #define SPORT2_MTCS0 0xFFC02540 /* SPORT2 Multi-Channel Transmit Select Register 0 */
753 #define SPORT2_MTCS1 0xFFC02544 /* SPORT2 Multi-Channel Transmit Select Register 1 */
754 #define SPORT2_MTCS2 0xFFC02548 /* SPORT2 Multi-Channel Transmit Select Register 2 */
755 #define SPORT2_MTCS3 0xFFC0254C /* SPORT2 Multi-Channel Transmit Select Register 3 */
756 #define SPORT2_MRCS0 0xFFC02550 /* SPORT2 Multi-Channel Receive Select Register 0 */
757 #define SPORT2_MRCS1 0xFFC02554 /* SPORT2 Multi-Channel Receive Select Register 1 */
758 #define SPORT2_MRCS2 0xFFC02558 /* SPORT2 Multi-Channel Receive Select Register 2 */
759 #define SPORT2_MRCS3 0xFFC0255C /* SPORT2 Multi-Channel Receive Select Register 3 */
762 /* SPORT3 Controller (0xFFC02600 - 0xFFC026FF) */
775 #define SPORT3_MCMC1 0xFFC02638 /* SPORT3 Multi-Channel Configuration Register 1 */
776 #define SPORT3_MCMC2 0xFFC0263C /* SPORT3 Multi-Channel Configuration Register 2 */
777 #define SPORT3_MTCS0 0xFFC02640 /* SPORT3 Multi-Channel Transmit Select Register 0 */
778 #define SPORT3_MTCS1 0xFFC02644 /* SPORT3 Multi-Channel Transmit Select Register 1 */
779 #define SPORT3_MTCS2 0xFFC02648 /* SPORT3 Multi-Channel Transmit Select Register 2 */
780 #define SPORT3_MTCS3 0xFFC0264C /* SPORT3 Multi-Channel Transmit Select Register 3 */
781 #define SPORT3_MRCS0 0xFFC02650 /* SPORT3 Multi-Channel Receive Select Register 0 */
782 #define SPORT3_MRCS1 0xFFC02654 /* SPORT3 Multi-Channel Receive Select Register 1 */
783 #define SPORT3_MRCS2 0xFFC02658 /* SPORT3 Multi-Channel Receive Select Register 2 */
784 #define SPORT3_MRCS3 0xFFC0265C /* SPORT3 Multi-Channel Receive Select Register 3 */
787 /* CAN Controller (0xFFC02A00 - 0xFFC02FFF) */
788 /* For Mailboxes 0-15 */
797 #define CAN_MBTIF1 0xFFC02A20 /* Mailbox Transmit Interrupt Flag reg 1 */
798 #define CAN_MBRIF1 0xFFC02A24 /* Mailbox Receive Interrupt Flag reg 1 */
799 #define CAN_MBIM1 0xFFC02A28 /* Mailbox Interrupt Mask reg 1 */
803 /* For Mailboxes 16-31 */
812 #define CAN_MBTIF2 0xFFC02A60 /* Mailbox Transmit Interrupt Flag reg 2 */
813 #define CAN_MBRIF2 0xFFC02A64 /* Mailbox Receive Interrupt Flag reg 2 */
814 #define CAN_MBIM2 0xFFC02A68 /* Mailbox Interrupt Mask reg 2 */
827 #define CAN_GIS 0xFFC02A94 /* Global Interrupt Status Register */
828 #define CAN_GIM 0xFFC02A98 /* Global Interrupt Mask Register */
829 #define CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */
831 #define CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */
840 #define CAN_AM00L 0xFFC02B00 /* Mailbox 0 Low Acceptance Mask */
841 #define CAN_AM00H 0xFFC02B04 /* Mailbox 0 High Acceptance Mask */
842 #define CAN_AM01L 0xFFC02B08 /* Mailbox 1 Low Acceptance Mask */
843 #define CAN_AM01H 0xFFC02B0C /* Mailbox 1 High Acceptance Mask */
844 #define CAN_AM02L 0xFFC02B10 /* Mailbox 2 Low Acceptance Mask */
845 #define CAN_AM02H 0xFFC02B14 /* Mailbox 2 High Acceptance Mask */
846 #define CAN_AM03L 0xFFC02B18 /* Mailbox 3 Low Acceptance Mask */
847 #define CAN_AM03H 0xFFC02B1C /* Mailbox 3 High Acceptance Mask */
848 #define CAN_AM04L 0xFFC02B20 /* Mailbox 4 Low Acceptance Mask */
849 #define CAN_AM04H 0xFFC02B24 /* Mailbox 4 High Acceptance Mask */
850 #define CAN_AM05L 0xFFC02B28 /* Mailbox 5 Low Acceptance Mask */
851 #define CAN_AM05H 0xFFC02B2C /* Mailbox 5 High Acceptance Mask */
852 #define CAN_AM06L 0xFFC02B30 /* Mailbox 6 Low Acceptance Mask */
853 #define CAN_AM06H 0xFFC02B34 /* Mailbox 6 High Acceptance Mask */
854 #define CAN_AM07L 0xFFC02B38 /* Mailbox 7 Low Acceptance Mask */
855 #define CAN_AM07H 0xFFC02B3C /* Mailbox 7 High Acceptance Mask */
856 #define CAN_AM08L 0xFFC02B40 /* Mailbox 8 Low Acceptance Mask */
857 #define CAN_AM08H 0xFFC02B44 /* Mailbox 8 High Acceptance Mask */
858 #define CAN_AM09L 0xFFC02B48 /* Mailbox 9 Low Acceptance Mask */
859 #define CAN_AM09H 0xFFC02B4C /* Mailbox 9 High Acceptance Mask */
860 #define CAN_AM10L 0xFFC02B50 /* Mailbox 10 Low Acceptance Mask */
861 #define CAN_AM10H 0xFFC02B54 /* Mailbox 10 High Acceptance Mask */
862 #define CAN_AM11L 0xFFC02B58 /* Mailbox 11 Low Acceptance Mask */
863 #define CAN_AM11H 0xFFC02B5C /* Mailbox 11 High Acceptance Mask */
864 #define CAN_AM12L 0xFFC02B60 /* Mailbox 12 Low Acceptance Mask */
865 #define CAN_AM12H 0xFFC02B64 /* Mailbox 12 High Acceptance Mask */
866 #define CAN_AM13L 0xFFC02B68 /* Mailbox 13 Low Acceptance Mask */
867 #define CAN_AM13H 0xFFC02B6C /* Mailbox 13 High Acceptance Mask */
868 #define CAN_AM14L 0xFFC02B70 /* Mailbox 14 Low Acceptance Mask */
869 #define CAN_AM14H 0xFFC02B74 /* Mailbox 14 High Acceptance Mask */
870 #define CAN_AM15L 0xFFC02B78 /* Mailbox 15 Low Acceptance Mask */
871 #define CAN_AM15H 0xFFC02B7C /* Mailbox 15 High Acceptance Mask */
873 #define CAN_AM16L 0xFFC02B80 /* Mailbox 16 Low Acceptance Mask */
874 #define CAN_AM16H 0xFFC02B84 /* Mailbox 16 High Acceptance Mask */
875 #define CAN_AM17L 0xFFC02B88 /* Mailbox 17 Low Acceptance Mask */
876 #define CAN_AM17H 0xFFC02B8C /* Mailbox 17 High Acceptance Mask */
877 #define CAN_AM18L 0xFFC02B90 /* Mailbox 18 Low Acceptance Mask */
878 #define CAN_AM18H 0xFFC02B94 /* Mailbox 18 High Acceptance Mask */
879 #define CAN_AM19L 0xFFC02B98 /* Mailbox 19 Low Acceptance Mask */
880 #define CAN_AM19H 0xFFC02B9C /* Mailbox 19 High Acceptance Mask */
881 #define CAN_AM20L 0xFFC02BA0 /* Mailbox 20 Low Acceptance Mask */
882 #define CAN_AM20H 0xFFC02BA4 /* Mailbox 20 High Acceptance Mask */
883 #define CAN_AM21L 0xFFC02BA8 /* Mailbox 21 Low Acceptance Mask */
884 #define CAN_AM21H 0xFFC02BAC /* Mailbox 21 High Acceptance Mask */
885 #define CAN_AM22L 0xFFC02BB0 /* Mailbox 22 Low Acceptance Mask */
886 #define CAN_AM22H 0xFFC02BB4 /* Mailbox 22 High Acceptance Mask */
887 #define CAN_AM23L 0xFFC02BB8 /* Mailbox 23 Low Acceptance Mask */
888 #define CAN_AM23H 0xFFC02BBC /* Mailbox 23 High Acceptance Mask */
889 #define CAN_AM24L 0xFFC02BC0 /* Mailbox 24 Low Acceptance Mask */
890 #define CAN_AM24H 0xFFC02BC4 /* Mailbox 24 High Acceptance Mask */
891 #define CAN_AM25L 0xFFC02BC8 /* Mailbox 25 Low Acceptance Mask */
892 #define CAN_AM25H 0xFFC02BCC /* Mailbox 25 High Acceptance Mask */
893 #define CAN_AM26L 0xFFC02BD0 /* Mailbox 26 Low Acceptance Mask */
894 #define CAN_AM26H 0xFFC02BD4 /* Mailbox 26 High Acceptance Mask */
895 #define CAN_AM27L 0xFFC02BD8 /* Mailbox 27 Low Acceptance Mask */
896 #define CAN_AM27H 0xFFC02BDC /* Mailbox 27 High Acceptance Mask */
897 #define CAN_AM28L 0xFFC02BE0 /* Mailbox 28 Low Acceptance Mask */
898 #define CAN_AM28H 0xFFC02BE4 /* Mailbox 28 High Acceptance Mask */
899 #define CAN_AM29L 0xFFC02BE8 /* Mailbox 29 Low Acceptance Mask */
900 #define CAN_AM29H 0xFFC02BEC /* Mailbox 29 High Acceptance Mask */
901 #define CAN_AM30L 0xFFC02BF0 /* Mailbox 30 Low Acceptance Mask */
902 #define CAN_AM30H 0xFFC02BF4 /* Mailbox 30 High Acceptance Mask */
903 #define CAN_AM31L 0xFFC02BF8 /* Mailbox 31 Low Acceptance Mask */
904 #define CAN_AM31H 0xFFC02BFC /* Mailbox 31 High Acceptance Mask */
906 /* CAN Acceptance Mask Macros */
1214 /* SWRST Mask */
1217 #define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
1222 #define BMODE 0x0006 /* Boot Mode - Latched During HW Reset From Mode Pins */
1226 /* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
1229 #define PLL_WAKEUP_IRQ 0x00000001 /* PLL Wakeup Interrupt Request */
1230 #define DMAC0_ERR_IRQ 0x00000002 /* DMA Controller 0 Error Interrupt Request */
1231 #define PPI_ERR_IRQ 0x00000004 /* PPI Error Interrupt Request */
1232 #define SPORT0_ERR_IRQ 0x00000008 /* SPORT0 Error Interrupt Request */
1233 #define SPORT1_ERR_IRQ 0x00000010 /* SPORT1 Error Interrupt Request */
1234 #define SPI0_ERR_IRQ 0x00000020 /* SPI0 Error Interrupt Request */
1235 #define UART0_ERR_IRQ 0x00000040 /* UART0 Error Interrupt Request */
1236 #define RTC_IRQ 0x00000080 /* Real-Time Clock Interrupt Request */
1237 #define DMA0_IRQ 0x00000100 /* DMA Channel 0 (PPI) Interrupt Request */
1238 #define DMA1_IRQ 0x00000200 /* DMA Channel 1 (SPORT0 RX) Interrupt Request */
1239 #define DMA2_IRQ 0x00000400 /* DMA Channel 2 (SPORT0 TX) Interrupt Request */
1240 #define DMA3_IRQ 0x00000800 /* DMA Channel 3 (SPORT1 RX) Interrupt Request */
1241 #define DMA4_IRQ 0x00001000 /* DMA Channel 4 (SPORT1 TX) Interrupt Request */
1242 #define DMA5_IRQ 0x00002000 /* DMA Channel 5 (SPI) Interrupt Request */
1243 #define DMA6_IRQ 0x00004000 /* DMA Channel 6 (UART RX) Interrupt Request */
1244 #define DMA7_IRQ 0x00008000 /* DMA Channel 7 (UART TX) Interrupt Request */
1245 #define TIMER0_IRQ 0x00010000 /* Timer 0 Interrupt Request */
1246 #define TIMER1_IRQ 0x00020000 /* Timer 1 Interrupt Request */
1247 #define TIMER2_IRQ 0x00040000 /* Timer 2 Interrupt Request */
1248 #define PFA_IRQ 0x00080000 /* Programmable Flag Interrupt Request A */
1249 #define PFB_IRQ 0x00100000 /* Programmable Flag Interrupt Request B */
1250 #define MDMA0_0_IRQ 0x00200000 /* MemDMA0 Stream 0 Interrupt Request */
1251 #define MDMA0_1_IRQ 0x00400000 /* MemDMA0 Stream 1 Interrupt Request */
1252 #define WDOG_IRQ 0x00800000 /* Software Watchdog Timer Interrupt Request */
1253 #define DMAC1_ERR_IRQ 0x01000000 /* DMA Controller 1 Error Interrupt Request */
1254 #define SPORT2_ERR_IRQ 0x02000000 /* SPORT2 Error Interrupt Request */
1255 #define SPORT3_ERR_IRQ 0x04000000 /* SPORT3 Error Interrupt Request */
1256 #define MXVR_SD_IRQ 0x08000000 /* MXVR Synchronous Data Interrupt Request */
1257 #define SPI1_ERR_IRQ 0x10000000 /* SPI1 Error Interrupt Request */
1258 #define SPI2_ERR_IRQ 0x20000000 /* SPI2 Error Interrupt Request */
1259 #define UART1_ERR_IRQ 0x40000000 /* UART1 Error Interrupt Request */
1260 #define UART2_ERR_IRQ 0x80000000 /* UART2 Error Interrupt Request */
1268 #define CAN_ERR_IRQ 0x00000001 /* CAN Error Interrupt Request */
1269 #define DMA8_IRQ 0x00000002 /* DMA Channel 8 (SPORT2 RX) Interrupt Request */
1270 #define DMA9_IRQ 0x00000004 /* DMA Channel 9 (SPORT2 TX) Interrupt Request */
1271 #define DMA10_IRQ 0x00000008 /* DMA Channel 10 (SPORT3 RX) Interrupt Request */
1272 #define DMA11_IRQ 0x00000010 /* DMA Channel 11 (SPORT3 TX) Interrupt Request */
1273 #define DMA12_IRQ 0x00000020 /* DMA Channel 12 Interrupt Request */
1274 #define DMA13_IRQ 0x00000040 /* DMA Channel 13 Interrupt Request */
1275 #define DMA14_IRQ 0x00000080 /* DMA Channel 14 (SPI1) Interrupt Request */
1276 #define DMA15_IRQ 0x00000100 /* DMA Channel 15 (SPI2) Interrupt Request */
1277 #define DMA16_IRQ 0x00000200 /* DMA Channel 16 (UART1 RX) Interrupt Request */
1278 #define DMA17_IRQ 0x00000400 /* DMA Channel 17 (UART1 TX) Interrupt Request */
1279 #define DMA18_IRQ 0x00000800 /* DMA Channel 18 (UART2 RX) Interrupt Request */
1280 #define DMA19_IRQ 0x00001000 /* DMA Channel 19 (UART2 TX) Interrupt Request */
1281 #define TWI0_IRQ 0x00002000 /* TWI0 Interrupt Request */
1282 #define TWI1_IRQ 0x00004000 /* TWI1 Interrupt Request */
1283 #define CAN_RX_IRQ 0x00008000 /* CAN Receive Interrupt Request */
1284 #define CAN_TX_IRQ 0x00010000 /* CAN Transmit Interrupt Request */
1285 #define MDMA1_0_IRQ 0x00020000 /* MemDMA1 Stream 0 Interrupt Request */
1286 #define MDMA1_1_IRQ 0x00040000 /* MemDMA1 Stream 1 Interrupt Request */
1287 #define MXVR_STAT_IRQ 0x00080000 /* MXVR Status Interrupt Request */
1288 #define MXVR_CM_IRQ 0x00100000 /* MXVR Control Message Interrupt Request */
1289 #define MXVR_AP_IRQ 0x00200000 /* MXVR Asynchronous Packet Interrupt */
1305 #define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
1307 #define SIC_MASK(x) (1 << ((x)&0x1Fu)) /* Mask Peripheral #x interrupt */
1308 #define SIC_UNMASK(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu))) /* Unmask Peripheral #x interrupt */
1310 #define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
1311 #define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
1333 /* previous versions of defBF539.h erroneously included DMA32 (PPI 32-bit DMA Enable) */
1337 #define DLEN_8 0x0 /* PPI Data Length mask for DLEN=8 */
1346 #define DLEN(x) ((((x)-9u) & 0x07u) << 11) /* PPI Data Length (only works for x=10-->x=16) */
1348 #define DLEN(x) ((((x)-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */
1370 #define PCAP8 0x0080 /* DMA 8-bit Operation Indicator */
1371 #define PCAP16 0x0100 /* DMA 16-bit Operation Indicator */
1372 #define PCAP32 0x0200 /* DMA 32-bit Operation Indicator */
1375 #define PMAP 0xF000 /* DMA Peripheral Map Field */
1421 #define TIMIL0 0x0001 /* Timer 0 Interrupt */
1422 #define TIMIL1 0x0002 /* Timer 1 Interrupt */
1423 #define TIMIL2 0x0004 /* Timer 2 Interrupt */
1492 #define AMBEN_P0 0x0001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enab…
1493 #define AMBEN_P1 0x0002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 e…
1494 #define AMBEN_P2 0x0003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabl…
1683 #define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
1684 #define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
1685 #define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
1718 #define PUPSD 0x00200000 /*Power-up start delay */
1719 #define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh …
1720 #define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */
1721 #define SRFS 0x01000000 /* Start SDRAM self-refresh mode */
1723 #define FBBRW 0x04000000 /* Fast back-to-back read write enable */
1746 #define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */
1750 /* ******************** TWO-WIRE INTERFACE (TWIx) MASKS ***********************/
1811 #define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
1812 #define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */