Lines Matching +full:spi +full:- +full:tx +full:- +full:bus +full:- +full:width
2 * Copyright 2005-2010 Analog Devices Inc.
4 * Licensed under the ADI BSD license or the GPL-2 (or later)
13 /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
21 /* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
33 /* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
38 /* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
47 /* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
50 #define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
52 #define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
61 /* SPI Controller (0xFFC00500 - 0xFFC005FF) */
63 #define SPI_CTL 0xFFC00500 /* SPI Control Register */
64 #define SPI_FLG 0xFFC00504 /* SPI Flag register */
65 #define SPI_STAT 0xFFC00508 /* SPI Status register */
66 #define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
67 #define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
68 #define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
71 /* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
75 #define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
80 #define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
85 #define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
90 #define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */
95 #define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */
100 #define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */
105 #define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */
110 #define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */
116 /* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
135 /* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
140 #define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register …
148 #define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
149 #define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
150 #define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
151 #define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
152 #define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
153 #define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
154 #define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
155 #define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
156 #define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
157 #define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
159 /* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
164 #define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register …
172 #define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
173 #define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
174 #define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
175 #define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
176 #define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
177 #define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
178 #define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
179 #define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
180 #define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
181 #define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
183 /* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
196 /* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
421 /* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
428 /* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
447 /* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
466 /* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
485 /* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
488 #define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
490 #define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
499 /* CAN Controller (0xFFC02A00 - 0xFFC02FFF) */
500 /* For Mailboxes 0-15 */
515 /* For Mailboxes 16-31 */
920 /* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
926 /* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
949 ** macro that shifts left to properly position the bit-field should be
963 #define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
968 #define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */
974 #define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */
975 #define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
976 #define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
977 #define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */
978 #define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
979 #define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
980 #define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
981 #define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
984 #define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */
985 #define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
986 #define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
987 #define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */
988 #define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
989 #define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
990 #define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
991 #define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
994 #define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */
995 #define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
996 #define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
997 #define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */
998 #define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
999 #define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
1000 #define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
1001 #define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
1004 #define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */
1005 #define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */
1006 #define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */
1007 #define P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */
1008 #define P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */
1009 #define P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */
1010 #define P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */
1011 #define P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */
1082 #define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */
1083 #define WDTH_CAP 0x0002 /* Width Capture Input Mode */
1291 #define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh …
1292 #define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
1293 #define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh …
1326 #define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) …
1327 #define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */
1328 #define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */
1329 #define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode …
1331 #define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write …
1333 #define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */
1334 #define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant …
1344 #define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */
1345 #define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */
1346 #define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */
1347 #define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */
1351 #define SDSRA 0x0002 /* SDRAM Self-Refresh Active */
1352 #define SDPUA 0x0004 /* SDRAM Power-Up Active */
1353 #define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */
1355 #define BGSTAT 0x0020 /* Bus Grant Status */
1369 #define PMAP_SPI 0x7000 /* SPI Port DMA …
1383 #define DMA32 0x0100 /* PPI 32-bit DMA Enable */
1406 /* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/
1430 #define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
1447 #define BUSBUSY 0x0100 /* Bus Busy Indicator */
1478 #define PJSE 0x0001 /* Port J SPI/SPORT Enable */
1482 #define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */
1484 #define PJCE_CAN 0x0002 /* Enable CAN RX/TX */
1488 #define PFDE_UART 0x0000 /* Enable UART0 RX/TX */
1492 #define PFTE_UART 0x0000 /* Enable UART1 RX/TX */
1495 #define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */
1499 #define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */
1503 #define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */
1523 /* entry addresses of the user-callable Boot ROM functions */