Lines Matching +full:spi +full:- +full:tx +full:- +full:bus +full:- +full:width
2 * System & MMR bit and Address definitions for ADSP-BF532
4 * Copyright 2005-2010 Analog Devices Inc.
6 * Licensed under the ADI BSD license or the GPL-2 (or later)
15 /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
17 #define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */
18 #define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */
19 #define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
20 #define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */
21 #define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
24 /* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
25 #define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */
35 /* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
40 /* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
49 /* UART Controller (0xFFC00400 - 0xFFC004FF) */
57 #define BFIN_UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
59 #define BFIN_UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
65 #define BFIN_UART_MSR 0xFFC00418 /* Modem Status Register (UNUSED in ADSP-BF532) */
70 /* SPI Controller (0xFFC00500 - 0xFFC005FF) */
72 #define SPI_CTL 0xFFC00500 /* SPI Control Register */
73 #define SPI_FLG 0xFFC00504 /* SPI Flag register */
74 #define SPI_STAT 0xFFC00508 /* SPI Status register */
75 #define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
76 #define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
77 #define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
80 /* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */
85 #define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
90 #define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
95 #define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
101 /* General Purpose IO (0xFFC00700 - 0xFFC007FF) */
121 /* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
126 #define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
134 #define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
135 #define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
136 #define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
137 #define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
138 #define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
139 #define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
140 #define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
141 #define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
142 #define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
143 #define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
145 /* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
150 #define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
158 #define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
159 #define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
160 #define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
161 #define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
162 #define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
163 #define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
164 #define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
165 #define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
166 #define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
167 #define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
169 /* Asynchronous Memory Controller - External Bus Interface Unit */
174 /* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
185 /* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
354 /* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */
374 #define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
379 #define BMODE 0x0006 /* Boot Mode - Latched During HW Reset From Mode Pins */
386 #define P0_IVG(x) ((x)-7) /* Peripheral #0 assigned IVG #x */
387 #define P1_IVG(x) ((x)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
388 #define P2_IVG(x) ((x)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
389 #define P3_IVG(x) ((x)-7) << 0xC /* Peripheral #3 assigned IVG #x */
390 #define P4_IVG(x) ((x)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
391 #define P5_IVG(x) ((x)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
392 #define P6_IVG(x) ((x)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
393 #define P7_IVG(x) ((x)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
397 #define P8_IVG(x) ((x)-7) /* Peripheral #8 assigned IVG #x */
398 #define P9_IVG(x) ((x)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
399 #define P10_IVG(x) ((x)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
400 #define P11_IVG(x) ((x)-7) << 0xC /* Peripheral #11 assigned IVG #x */
401 #define P12_IVG(x) ((x)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
402 #define P13_IVG(x) ((x)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
403 #define P14_IVG(x) ((x)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
404 #define P15_IVG(x) ((x)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
407 #define P16_IVG(x) ((x)-7) /* Peripheral #16 assigned IVG #x */
408 #define P17_IVG(x) ((x)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
409 #define P18_IVG(x) ((x)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
410 #define P19_IVG(x) ((x)-7) << 0xC /* Peripheral #19 assigned IVG #x */
411 #define P20_IVG(x) ((x)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
412 #define P21_IVG(x) ((x)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
413 #define P22_IVG(x) ((x)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
414 #define P23_IVG(x) ((x)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
437 #define DMA32 0x00000100 /* PPI 32-bit DMA Enable */
449 #define DLEN(x) (((x-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */
468 #define PCAP8 0x00000080 /* DMA 8-bit Operation Indicator */
469 #define PCAP16 0x00000100 /* DMA 16-bit Operation Indicator */
470 #define PCAP32 0x00000200 /* DMA 32-bit Operation Indicator */
480 #define PMAP_SPI 0x5000 /* PMAP SPI DMA */
574 #define AMBEN_P0 0x00000001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 …
575 …e AMBEN_P1 0x00000002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 en…
576 #define AMBEN_P2 0x00000003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) e…
766 #define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
767 #define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
768 #define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
801 #define PUPSD 0x00200000 /*Power-up start delay */
802 #define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh c…
803 #define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */
804 #define SRFS 0x01000000 /* Start SDRAM self-refresh mode */
806 #define FBBRW 0x04000000 /* Fast back-to-back read write enable */
809 #define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */
817 #define EBCAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
818 #define EBCAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */
819 #define EBCAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */
820 #define EBCAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */
827 #define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */
828 #define BGSTAT 0x00000020 /* Bus granted */