Lines Matching full:read
376 #define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
472 #define PCAPRD 0x00000800 /* DMA Read Operation Indicator */
581 #define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */
582 #define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */
583 #define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */
584 #define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */
585 #define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
586 #define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
587 #define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
588 #define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
589 #define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycl…
590 #define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycl…
591 #define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycl…
592 #define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycl…
593 #define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */
594 #define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */
595 #define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */
596 #define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */
597 #define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */
598 #define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */
599 #define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */
600 #define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */
601 #define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */
602 #define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */
603 #define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */
604 #define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */
605 #define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */
606 #define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */
607 #define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */
625 #define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */
626 #define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */
627 #define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */
628 #define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */
629 #define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cy…
630 #define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cy…
631 #define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cy…
632 #define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cy…
633 #define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1…
634 #define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2…
635 #define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3…
636 #define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0…
637 #define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */
638 #define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */
639 #define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */
640 #define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */
641 #define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */
642 #define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */
643 #define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */
644 #define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */
645 #define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */
646 #define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */
647 #define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */
648 #define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */
649 #define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */
650 #define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */
651 #define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */
671 #define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */
672 #define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */
673 #define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */
674 #define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */
675 #define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cy…
676 #define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cy…
677 #define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cy…
678 #define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cy…
679 #define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1…
680 #define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2…
681 #define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3…
682 #define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0…
683 #define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */
684 #define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */
685 #define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */
686 #define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */
687 #define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */
688 #define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */
689 #define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */
690 #define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */
691 #define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */
692 #define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */
693 #define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */
694 #define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */
695 #define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */
696 #define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */
697 #define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */
715 #define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */
716 #define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */
717 #define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */
718 #define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */
719 #define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cy…
720 #define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cy…
721 #define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cy…
722 #define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cy…
723 #define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1…
724 #define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2…
725 #define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3…
726 #define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0…
727 #define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */
728 #define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */
729 #define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */
730 #define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */
731 #define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */
732 #define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */
733 #define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */
734 #define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */
735 #define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */
736 #define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */
737 #define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */
738 #define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */
739 #define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */
740 #define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */
741 #define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */
806 #define FBBRW 0x04000000 /* Fast back-to-back read write enable */