Lines Matching +full:write +full:- +full:to +full:- +full:write
2 * System & MMR bit and Address definitions for ADSP-BF532
4 * Copyright 2005-2010 Analog Devices Inc.
6 * Licensed under the ADI BSD license or the GPL-2 (or later)
15 /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
17 #define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */
18 #define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */
19 #define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
20 #define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */
21 #define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
24 /* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
25 #define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */
35 /* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
40 /* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
49 /* UART Controller (0xFFC00400 - 0xFFC004FF) */
53 * So we define blackfin uart regs to BFIN_UART_*.
57 #define BFIN_UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
59 #define BFIN_UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
65 #define BFIN_UART_MSR 0xFFC00418 /* Modem Status Register (UNUSED in ADSP-BF532) */
70 /* SPI Controller (0xFFC00500 - 0xFFC005FF) */
80 /* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */
101 /* General Purpose IO (0xFFC00700 - 0xFFC007FF) */
103 #define FIO_FLAG_D 0xFFC00700 /* Flag Mask to directly specify state of pins */
106 #define FIO_FLAG_T 0xFFC0070C /* Flag Mask to directly toggle state of pins */
121 /* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
134 #define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
135 #define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
136 #define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
137 #define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
138 #define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
139 #define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
140 #define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
141 #define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
142 #define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
143 #define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
145 /* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
158 #define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
159 #define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
160 #define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
161 #define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
162 #define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
163 #define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
164 #define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
165 #define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
166 #define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
167 #define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
169 /* Asynchronous Memory Controller - External Bus Interface Unit */
174 /* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
185 /* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
354 /* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */
374 #define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
379 #define BMODE 0x0006 /* Boot Mode - Latched During HW Reset From Mode Pins */
386 #define P0_IVG(x) ((x)-7) /* Peripheral #0 assigned IVG #x */
387 #define P1_IVG(x) ((x)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
388 #define P2_IVG(x) ((x)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
389 #define P3_IVG(x) ((x)-7) << 0xC /* Peripheral #3 assigned IVG #x */
390 #define P4_IVG(x) ((x)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
391 #define P5_IVG(x) ((x)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
392 #define P6_IVG(x) ((x)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
393 #define P7_IVG(x) ((x)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
397 #define P8_IVG(x) ((x)-7) /* Peripheral #8 assigned IVG #x */
398 #define P9_IVG(x) ((x)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
399 #define P10_IVG(x) ((x)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
400 #define P11_IVG(x) ((x)-7) << 0xC /* Peripheral #11 assigned IVG #x */
401 #define P12_IVG(x) ((x)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
402 #define P13_IVG(x) ((x)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
403 #define P14_IVG(x) ((x)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
404 #define P15_IVG(x) ((x)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
407 #define P16_IVG(x) ((x)-7) /* Peripheral #16 assigned IVG #x */
408 #define P17_IVG(x) ((x)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
409 #define P18_IVG(x) ((x)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
410 #define P19_IVG(x) ((x)-7) << 0xC /* Peripheral #19 assigned IVG #x */
411 #define P20_IVG(x) ((x)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
412 #define P21_IVG(x) ((x)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
413 #define P22_IVG(x) ((x)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
414 #define P23_IVG(x) ((x)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
437 #define DMA32 0x00000100 /* PPI 32-bit DMA Enable */
449 #define DLEN(x) (((x-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */
468 #define PCAP8 0x00000080 /* DMA 8-bit Operation Indicator */
469 #define PCAP16 0x00000100 /* DMA 16-bit Operation Indicator */
470 #define PCAP32 0x00000200 /* DMA 32-bit Operation Indicator */
471 #define PCAPWR 0x00000400 /* DMA Write Operation Indicator */
574 #define AMBEN_P0 0x00000001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 …
575 …e AMBEN_P1 0x00000002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 en…
576 #define AMBEN_P2 0x00000003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) e…
581 #define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */
582 #define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */
583 #define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */
584 #define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */
585 #define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
586 #define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
587 #define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
588 #define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
589 #define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycl…
590 #define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycl…
591 #define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycl…
592 #define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycl…
608 #define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */
609 #define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */
610 #define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */
611 #define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */
612 #define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */
613 #define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */
614 #define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */
615 #define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */
616 #define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */
617 #define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */
618 #define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */
619 #define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */
620 #define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */
621 #define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */
622 #define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */
625 #define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */
626 #define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */
627 #define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */
628 #define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */
629 #define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cy…
630 #define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cy…
631 #define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cy…
632 #define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cy…
633 #define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1…
634 #define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2…
635 #define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3…
636 #define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0…
652 #define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */
653 #define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */
654 #define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */
655 #define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */
656 #define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */
657 #define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */
658 #define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */
659 #define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */
660 #define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */
661 #define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */
662 #define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */
663 #define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */
664 #define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */
665 #define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */
666 #define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */
671 #define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */
672 #define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */
673 #define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */
674 #define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */
675 #define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cy…
676 #define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cy…
677 #define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cy…
678 #define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cy…
679 #define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1…
680 #define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2…
681 #define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3…
682 #define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0…
698 #define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */
699 #define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */
700 #define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */
701 #define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */
702 #define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */
703 #define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */
704 #define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */
705 #define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */
706 #define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */
707 #define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */
708 #define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */
709 #define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */
710 #define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */
711 #define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */
712 #define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */
715 #define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */
716 #define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */
717 #define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */
718 #define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */
719 #define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cy…
720 #define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cy…
721 #define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cy…
722 #define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cy…
723 #define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1…
724 #define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2…
725 #define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3…
726 #define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0…
742 #define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */
743 #define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */
744 #define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */
745 #define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */
746 #define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */
747 #define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */
748 #define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */
749 #define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */
750 #define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */
751 #define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */
752 #define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */
753 #define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */
754 #define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */
755 #define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */
756 #define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */
766 #define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
767 #define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
768 #define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
801 #define PUPSD 0x00200000 /*Power-up start delay */
802 #define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh c…
803 #define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */
804 #define SRFS 0x01000000 /* Start SDRAM self-refresh mode */
806 #define FBBRW 0x04000000 /* Fast back-to-back read write enable */
827 #define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */