Lines Matching full:for
17 #define USB_INTRTX 0xffc03808 /* Interrupt register for endpoint 0 and Tx …
18 #define USB_INTRRX 0xffc0380c /* Interrupt register for Rx endpoints 1 to …
19 #define USB_INTRTXE 0xffc03810 /* Interrupt enable register for IntrTx */
20 #define USB_INTRRXE 0xffc03814 /* Interrupt enable register for IntrRx */
21 #define USB_INTRUSB 0xffc03818 /* Interrupt register for common USB interru…
22 #define USB_INTRUSBE 0xffc0381c /* Interrupt enable register for IntrUSB */
24 #define USB_INDEX 0xffc03824 /* Index register for selecting the indexed …
27 #define USB_GLOBAL_CTL 0xffc03830 /* Global Clock Control for the core */
31 #define USB_TX_MAX_PACKET 0xffc03840 /* Maximum packet size for Host Tx endpoint …
32 … USB_CSR0 0xffc03844 /* Control Status register for endpoint 0 and Control Status register fo…
33 … USB_TXCSR 0xffc03844 /* Control Status register for endpoint 0 and Control Status register fo…
34 #define USB_RX_MAX_PACKET 0xffc03848 /* Maximum packet size for Host Rx endpoint …
35 #define USB_RXCSR 0xffc0384c /* Control Status register for Host Rx endpo…
38 …ffc03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoin…
39 …3858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
40 …3858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
41 …ffc0385c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoin…
42 #define USB_RXINTERVAL 0xffc03860 /* Sets the polling interval for Interrupt a…
65 #define USB_VPLEN 0xffc0394c /* Determines duration of VBUS pulse for VBU…
66 #define USB_HS_EOF1 0xffc03950 /* Time buffer for High-Speed transactions */
67 #define USB_FS_EOF1 0xffc03954 /* Time buffer for Full-Speed transactions */
68 #define USB_LS_EOF1 0xffc03958 /* Time buffer for Low-Speed transactions */
70 /* (APHY_CNTRL is for ADI usage only) */
74 /* (APHY_CALIB is for ADI usage only) */
80 /* (PHY_TEST is for ADI usage only) */
82 #define USB_PHY_TEST 0xffc039ec /* Used for reducing simulation time and sim…
84 #define USB_PLLOSC_CTRL 0xffc039f0 /* Used to program different parameters for …
85 #define USB_SRP_CLKDIV 0xffc039f4 /* Used to program clock divide value for th…
89 #define USB_EP_NI0_TXMAXP 0xffc03a00 /* Maximum packet size for Host Tx endpoint0…
90 #define USB_EP_NI0_TXCSR 0xffc03a04 /* Control Status register for endpoint 0 */
91 #define USB_EP_NI0_RXMAXP 0xffc03a08 /* Maximum packet size for Host Rx endpoint0…
92 #define USB_EP_NI0_RXCSR 0xffc03a0c /* Control Status register for Host Rx endpo…
94 …ffc03a14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoin…
96 …ffc03a1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoin…
97 …20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout …
102 #define USB_EP_NI1_TXMAXP 0xffc03a40 /* Maximum packet size for Host Tx endpoint1…
103 #define USB_EP_NI1_TXCSR 0xffc03a44 /* Control Status register for endpoint1 */
104 #define USB_EP_NI1_RXMAXP 0xffc03a48 /* Maximum packet size for Host Rx endpoint1…
105 #define USB_EP_NI1_RXCSR 0xffc03a4c /* Control Status register for Host Rx endpo…
107 …ffc03a54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoin…
109 …ffc03a5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoin…
110 …60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout …
115 #define USB_EP_NI2_TXMAXP 0xffc03a80 /* Maximum packet size for Host Tx endpoint2…
116 #define USB_EP_NI2_TXCSR 0xffc03a84 /* Control Status register for endpoint2 */
117 #define USB_EP_NI2_RXMAXP 0xffc03a88 /* Maximum packet size for Host Rx endpoint2…
118 #define USB_EP_NI2_RXCSR 0xffc03a8c /* Control Status register for Host Rx endpo…
120 …ffc03a94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoin…
122 …ffc03a9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoin…
123 …a0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout …
128 #define USB_EP_NI3_TXMAXP 0xffc03ac0 /* Maximum packet size for Host Tx endpoint3…
129 #define USB_EP_NI3_TXCSR 0xffc03ac4 /* Control Status register for endpoint3 */
130 #define USB_EP_NI3_RXMAXP 0xffc03ac8 /* Maximum packet size for Host Rx endpoint3…
131 #define USB_EP_NI3_RXCSR 0xffc03acc /* Control Status register for Host Rx endpo…
133 …ffc03ad4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoin…
135 …ffc03adc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoin…
136 …e0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout …
141 #define USB_EP_NI4_TXMAXP 0xffc03b00 /* Maximum packet size for Host Tx endpoint4…
142 #define USB_EP_NI4_TXCSR 0xffc03b04 /* Control Status register for endpoint4 */
143 #define USB_EP_NI4_RXMAXP 0xffc03b08 /* Maximum packet size for Host Rx endpoint4…
144 #define USB_EP_NI4_RXCSR 0xffc03b0c /* Control Status register for Host Rx endpo…
146 …ffc03b14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoin…
148 …ffc03b1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoin…
149 …20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout …
154 #define USB_EP_NI5_TXMAXP 0xffc03b40 /* Maximum packet size for Host Tx endpoint5…
155 #define USB_EP_NI5_TXCSR 0xffc03b44 /* Control Status register for endpoint5 */
156 #define USB_EP_NI5_RXMAXP 0xffc03b48 /* Maximum packet size for Host Rx endpoint5…
157 #define USB_EP_NI5_RXCSR 0xffc03b4c /* Control Status register for Host Rx endpo…
159 …ffc03b54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoin…
161 …ffc03b5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoin…
162 …60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout …
167 #define USB_EP_NI6_TXMAXP 0xffc03b80 /* Maximum packet size for Host Tx endpoint6…
168 #define USB_EP_NI6_TXCSR 0xffc03b84 /* Control Status register for endpoint6 */
169 #define USB_EP_NI6_RXMAXP 0xffc03b88 /* Maximum packet size for Host Rx endpoint6…
170 #define USB_EP_NI6_RXCSR 0xffc03b8c /* Control Status register for Host Rx endpo…
172 …ffc03b94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoin…
174 …ffc03b9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoin…
175 …a0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout …
180 #define USB_EP_NI7_TXMAXP 0xffc03bc0 /* Maximum packet size for Host Tx endpoint7…
181 #define USB_EP_NI7_TXCSR 0xffc03bc4 /* Control Status register for endpoint7 */
182 #define USB_EP_NI7_RXMAXP 0xffc03bc8 /* Maximum packet size for Host Rx endpoint7…
183 #define USB_EP_NI7_RXCSR 0xffc03bcc /* Control Status register for Host Rx endpo…
185 …ffc03bd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoin…
187 …ffc03bdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoin…
188 …e0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout …
191 #define USB_DMA_INTERRUPT 0xffc03c00 /* Indicates pending interrupts for the DMA …
196 …DDRLOW 0xffc03c08 /* Lower 16-bits of memory source/destination address for DMA master channel …
197 …DRHIGH 0xffc03c0c /* Upper 16-bits of memory source/destination address for DMA master channel …
198 …_DMA0COUNTLOW 0xffc03c10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel …
199 …DMA0COUNTHIGH 0xffc03c14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel …
204 …DDRLOW 0xffc03c28 /* Lower 16-bits of memory source/destination address for DMA master channel …
205 …DRHIGH 0xffc03c2c /* Upper 16-bits of memory source/destination address for DMA master channel …
206 …_DMA1COUNTLOW 0xffc03c30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel …
207 …DMA1COUNTHIGH 0xffc03c34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel …
212 …DDRLOW 0xffc03c48 /* Lower 16-bits of memory source/destination address for DMA master channel …
213 …DRHIGH 0xffc03c4c /* Upper 16-bits of memory source/destination address for DMA master channel …
214 …_DMA2COUNTLOW 0xffc03c50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel …
215 …DMA2COUNTHIGH 0xffc03c54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel …
220 …DDRLOW 0xffc03c68 /* Lower 16-bits of memory source/destination address for DMA master channel …
221 …DRHIGH 0xffc03c6c /* Upper 16-bits of memory source/destination address for DMA master channel …
222 …_DMA3COUNTLOW 0xffc03c70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel …
223 …DMA3COUNTHIGH 0xffc03c74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel …
228 …DDRLOW 0xffc03c88 /* Lower 16-bits of memory source/destination address for DMA master channel …
229 …DRHIGH 0xffc03c8c /* Upper 16-bits of memory source/destination address for DMA master channel …
230 …_DMA4COUNTLOW 0xffc03c90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel …
231 …DMA4COUNTHIGH 0xffc03c94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel …
236 …DDRLOW 0xffc03ca8 /* Lower 16-bits of memory source/destination address for DMA master channel …
237 …DRHIGH 0xffc03cac /* Upper 16-bits of memory source/destination address for DMA master channel …
238 …_DMA5COUNTLOW 0xffc03cb0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel …
239 …DMA5COUNTHIGH 0xffc03cb4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel …
244 …DDRLOW 0xffc03cc8 /* Lower 16-bits of memory source/destination address for DMA master channel …
245 …DRHIGH 0xffc03ccc /* Upper 16-bits of memory source/destination address for DMA master channel …
246 …_DMA6COUNTLOW 0xffc03cd0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel …
247 …DMA6COUNTHIGH 0xffc03cd4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel …
252 …DDRLOW 0xffc03ce8 /* Lower 16-bits of memory source/destination address for DMA master channel …
253 …DRHIGH 0xffc03cec /* Upper 16-bits of memory source/destination address for DMA master channel …
254 …_DMA7COUNTLOW 0xffc03cf0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel …
255 …DMA7COUNTHIGH 0xffc03cf4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel …
257 /* Bit masks for USB_FADDR */
261 /* Bit masks for USB_POWER */
280 /* Bit masks for USB_INTRTX */
299 /* Bit masks for USB_INTRRX */
316 /* Bit masks for USB_INTRTXE */
335 /* Bit masks for USB_INTRRXE */
352 /* Bit masks for USB_INTRUSB */
371 /* Bit masks for USB_INTRUSBE */
390 /* Bit masks for USB_FRAME */
394 /* Bit masks for USB_INDEX */
398 /* Bit masks for USB_GLOBAL_CTL */
431 /* Bit masks for USB_OTG_DEV_CTL */
450 /* Bit masks for USB_OTG_VBUS_IRQ */
456 #define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging V…
458 #define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBU…
465 /* Bit masks for USB_OTG_VBUS_MASK */
480 /* Bit masks for USB_CSR0 */
513 /* Bit masks for USB_COUNT0 */
517 /* Bit masks for USB_NAKLIMIT0 */
521 /* Bit masks for USB_TX_MAX_PACKET */
525 /* Bit masks for USB_RX_MAX_PACKET */
529 /* Bit masks for USB_TXCSR */
535 #define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
551 #define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
564 /* Bit masks for USB_TXCOUNT */
568 /* Bit masks for USB_RXCSR */
574 #define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
592 #define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
598 #define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
611 /* Bit masks for USB_RXCOUNT */
615 /* Bit masks for USB_TXTYPE */
620 /* Bit masks for USB_TXINTERVAL */
622 #define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
624 /* Bit masks for USB_RXTYPE */
629 /* Bit masks for USB_RXINTERVAL */
631 #define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
633 /* Bit masks for USB_DMA_INTERRUPT */
652 /* Bit masks for USB_DMAxCONTROL */
666 /* Bit masks for USB_DMAxADDRHIGH */
668 …DDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master chan…
670 /* Bit masks for USB_DMAxADDRLOW */
672 …ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master chan…
674 /* Bit masks for USB_DMAxCOUNTHIGH */
676 #define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DM…
678 /* Bit masks for USB_DMAxCOUNTLOW */
680 #define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DM…