Lines Matching +full:write +full:- +full:to +full:- +full:write
2 * Copyright 2007-2010 Analog Devices Inc.
4 * Licensed under the ADI BSD license or the GPL-2 (or later)
11 /* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF52x */
16 /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
25 /* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
38 /* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
48 /* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
54 /* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
64 /* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
67 #define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
69 #define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
79 /* SPI Controller (0xFFC00500 - 0xFFC005FF) */
90 /* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
136 /* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
156 /* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
169 #define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
170 #define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
171 #define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
172 #define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
173 #define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
174 #define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
175 #define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
176 #define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
177 #define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
178 #define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
181 /* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
194 #define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
195 #define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
196 #define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
197 #define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
198 #define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
199 #define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
200 #define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
201 #define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
202 #define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
203 #define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
206 /* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
220 /* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
446 /* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
454 /* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
474 /* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
494 /* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
514 /* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
517 #define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
519 #define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
529 /* Omit CAN register sets from the defBF534.h (CAN is not in the ADSP-BF52x processor) */
531 /* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
538 /* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
555 /* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
576 ** Disclaimer: All macros are intended to make C and Assembly code more readable.
579 ** macro that shifts left to properly position the bit-field should be
580 ** used as part of an OR to initialize a register and NOT as a dynamic
593 #define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
598 #define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */
650 #define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */
651 #define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
652 #define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
653 #define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */
654 #define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
655 #define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
656 #define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
657 #define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
660 #define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */
661 #define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
662 #define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
663 #define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */
664 #define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
665 #define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
666 #define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
667 #define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
670 #define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */
671 #define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
672 #define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
673 #define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */
674 #define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
675 #define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
676 #define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
677 #define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
680 #define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */
681 #define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */
682 #define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */
683 #define P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */
684 #define P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */
685 #define P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */
686 #define P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */
687 #define P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */
760 #define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */
785 #define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */
786 #define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */
787 #define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */
788 #define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */
789 #define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */
790 #define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */
791 #define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */
792 #define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */
793 #define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */
794 #define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */
795 #define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */
796 #define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */
812 #define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */
813 #define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */
814 #define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */
815 #define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */
816 #define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */
817 #define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */
818 #define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */
819 #define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */
820 #define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */
821 #define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */
822 #define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */
823 #define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */
824 #define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */
825 #define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */
826 #define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */
830 #define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */
831 #define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */
832 #define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */
833 #define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */
834 #define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */
835 #define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */
836 #define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */
837 #define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */
838 #define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */
839 #define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */
840 #define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */
841 #define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */
857 #define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */
858 #define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */
859 #define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */
860 #define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */
861 #define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */
862 #define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */
863 #define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */
864 #define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */
865 #define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */
866 #define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */
867 #define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */
868 #define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */
869 #define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */
870 #define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */
871 #define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */
876 #define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */
877 #define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */
878 #define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */
879 #define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */
880 #define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */
881 #define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */
882 #define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */
883 #define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */
884 #define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */
885 #define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */
886 #define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */
887 #define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */
903 #define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */
904 #define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */
905 #define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */
906 #define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */
907 #define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */
908 #define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */
909 #define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */
910 #define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */
911 #define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */
912 #define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */
913 #define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */
914 #define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */
915 #define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */
916 #define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */
917 #define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */
921 #define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */
922 #define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */
923 #define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */
924 #define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */
925 #define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */
926 #define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */
927 #define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */
928 #define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */
929 #define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */
930 #define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */
931 #define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */
932 #define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */
948 #define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */
949 #define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */
950 #define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */
951 #define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */
952 #define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */
953 #define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */
954 #define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */
955 #define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */
956 #define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */
957 #define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */
958 #define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */
959 #define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */
960 #define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */
961 #define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */
962 #define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */
970 #define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
971 #define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
972 #define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
1005 #define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */
1006 #define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */
1007 #define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */
1008 #define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */
1010 #define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */
1012 #define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */
1030 #define SDSRA 0x0002 /* SDRAM Self-Refresh Active */
1031 #define SDPUA 0x0004 /* SDRAM Power-Up Active */
1032 #define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */
1041 #define PMAP 0xF000 /* Peripheral Mapped To This Channel */
1063 #define DMA32 0x0100 /* PPI 32-bit DMA Enable */
1087 /* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/
1115 #define DCNT 0x3FC0 /* Data Bytes To Transfer */
1125 #define BUFWRERR 0x0020 /* Buffer Write Error */
1149 #define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
1150 #define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
1154 #define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
1155 #define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
1207 /* entry addresses of the user-callable Boot ROM functions */
1256 /* OTP Read/Write Data Buffer Registers */
1258 … OTP_DATA0 0xffc03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffe…
1259 … OTP_DATA1 0xffc03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffe…
1260 … OTP_DATA2 0xffc03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffe…
1261 … OTP_DATA3 0xffc0368c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffe…
1279 #define NFC_DATA_WR 0xffc03748 /* NAND Data Write Register */
1303 #define HOST_CNTR_EHW 0x100 /* Enable Host Write */