Lines Matching full:read
595 #define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
785 #define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */
786 #define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */
787 #define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */
788 #define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */
789 #define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */
790 #define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */
791 #define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */
792 #define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */
793 #define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */
794 #define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */
795 #define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */
796 #define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */
797 #define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */
798 #define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */
799 #define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */
800 #define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */
801 #define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */
802 #define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */
803 #define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */
804 #define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */
805 #define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */
806 #define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */
807 #define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */
808 #define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */
809 #define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */
810 #define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */
811 #define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */
830 #define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */
831 #define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */
832 #define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */
833 #define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */
834 #define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */
835 #define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */
836 #define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */
837 #define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */
838 #define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */
839 #define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */
840 #define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */
841 #define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */
842 #define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */
843 #define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */
844 #define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */
845 #define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */
846 #define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */
847 #define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */
848 #define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */
849 #define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */
850 #define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */
851 #define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */
852 #define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */
853 #define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */
854 #define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */
855 #define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */
856 #define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */
876 #define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */
877 #define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */
878 #define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */
879 #define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */
880 #define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */
881 #define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */
882 #define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */
883 #define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */
884 #define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */
885 #define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */
886 #define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */
887 #define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */
888 #define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */
889 #define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */
890 #define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */
891 #define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */
892 #define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */
893 #define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */
894 #define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */
895 #define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */
896 #define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */
897 #define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */
898 #define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */
899 #define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */
900 #define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */
901 #define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */
902 #define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */
921 #define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */
922 #define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */
923 #define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */
924 #define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */
925 #define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */
926 #define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */
927 #define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */
928 #define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */
929 #define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */
930 #define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */
931 #define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */
932 #define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */
933 #define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */
934 #define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */
935 #define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */
936 #define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */
937 #define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */
938 #define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */
939 #define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */
940 #define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */
941 #define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */
942 #define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */
943 #define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */
944 #define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */
945 #define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */
946 #define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */
947 #define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */
1010 #define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */
1124 #define BUFRDERR 0x0010 /* Buffer Read Error */
1154 #define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
1155 #define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
1256 /* OTP Read/Write Data Buffer Registers */
1258 … OTP_DATA0 0xffc03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1259 … OTP_DATA1 0xffc03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1260 … OTP_DATA2 0xffc03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1261 … OTP_DATA3 0xffc0368c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1276 #define NFC_READ 0xffc0372c /* NAND Read Data Register */
1280 #define NFC_DATA_RD 0xffc0374c /* NAND Data Read Register */
1284 /* and MULTI BIT READ MACROS */
1305 #define HOST_CNTR_EHR 0x200 /* Enable Host Read */
1332 #define HOST_STAT_HOSTRD_DONE 0x8000 /* Host Read Completion Interrupt */