Lines Matching +full:spi +full:- +full:tx +full:- +full:bus +full:- +full:width
2 * Copyright 2008-2010 Analog Devices Inc.
4 * Licensed under the ADI BSD license or the GPL-2 (or later)
11 /* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF51x */
14 /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
22 /* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
35 /* SIC Additions to ADSP-BF51x (0xFFC0014C - 0xFFC00162) */
45 /* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
51 /* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
61 /* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
64 #define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
66 #define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
75 /* SPI0 Controller (0xFFC00500 - 0xFFC005FF) */
77 #define SPI0_CTL 0xFFC00500 /* SPI Control Register */
78 #define SPI0_FLG 0xFFC00504 /* SPI Flag register */
79 #define SPI0_STAT 0xFFC00508 /* SPI Status register */
80 #define SPI0_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
81 #define SPI0_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
82 #define SPI0_BAUD 0xFFC00514 /* SPI Baud rate Register */
85 /* SPI1 Controller (0xFFC03400 - 0xFFC034FF) */
87 #define SPI1_CTL 0xFFC03400 /* SPI Control Register */
88 #define SPI1_FLG 0xFFC03404 /* SPI Flag register */
89 #define SPI1_STAT 0xFFC03408 /* SPI Status register */
90 #define SPI1_TDBR 0xFFC0340C /* SPI Transmit Data Buffer Register */
91 #define SPI1_RDBR 0xFFC03410 /* SPI Receive Data Buffer Register */
92 #define SPI1_BAUD 0xFFC03414 /* SPI Baud rate Register */
95 /* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
99 #define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
104 #define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
109 #define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
114 #define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */
119 #define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */
124 #define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */
129 #define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */
134 #define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */
140 /* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
159 /* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
164 #define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
172 #define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
173 #define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
174 #define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
175 #define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
176 #define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
177 #define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
178 #define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
179 #define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
180 #define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
181 #define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
183 /* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
188 #define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
196 #define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
197 #define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
198 #define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
199 #define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
200 #define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
201 #define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
202 #define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
203 #define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
204 #define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
205 #define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
207 /* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
220 /* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
446 /* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
454 /* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
474 /* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
494 /* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
514 /* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
517 #define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
519 #define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
529 /* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
536 /* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
554 /* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
578 ** macro that shifts left to properly position the bit-field should be
592 #define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
597 #define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */
608 #define IRQ_ERROR2 0x00000004 /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */
612 #define IRQ_DMA4 0x00000040 /* DMA Channel 4 (SPORT0 TX) Interrupt */
615 #define IRQ_DMA6 0x00000100 /* DMA Channel 6 (SPORT1 TX) Interrupt */
617 #define IRQ_DMA7 0x00000400 /* DMA Channel 7 (SPI) Interrupt */
619 #define IRQ_DMA9 0x00001000 /* DMA Channel 9 (UART0 TX) Interrupt */
621 #define IRQ_DMA11 0x00004000 /* DMA Channel 11 (UART1 TX) Interrupt */
627 #define IRQ_DMA2 0x00040000 /* DMA Channel 2 (Ethernet TX) Interrupt */
641 #define IRQ_DMA13 0x20000000 /* DMA Channels 13 (MDMA1 Destination) TX Interrupt */
643 #define IRQ_DMA15 0x40000000 /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */
649 #define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */
650 #define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
651 #define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
652 #define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */
653 #define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
654 #define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
655 #define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
656 #define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
659 #define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */
660 #define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
661 #define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
662 #define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */
663 #define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
664 #define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
665 #define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
666 #define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
669 #define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */
670 #define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
671 #define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
672 #define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */
673 #define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
674 #define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
675 #define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
676 #define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
679 #define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */
680 #define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */
681 #define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */
682 #define P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */
683 #define P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */
684 #define P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */
685 #define P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */
686 #define P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */
759 #define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */
760 #define WDTH_CAP 0x0002 /* Width Capture Input Mode */
969 #define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
970 #define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
971 #define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
1004 #define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */
1005 #define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */
1006 #define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */
1007 #define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */
1009 #define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */
1011 #define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */
1012 #define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */
1022 #define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */
1023 #define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */
1024 #define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */
1025 #define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */
1029 #define SDSRA 0x0002 /* SDRAM Self-Refresh Active */
1030 #define SDPUA 0x0004 /* SDRAM Power-Up Active */
1031 #define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */
1033 #define BGSTAT 0x0020 /* Bus Grant Status */
1048 #define PMAP_SPI 0x7000 /* SPI Port DMA */
1062 #define DMA32 0x0100 /* PPI 32-bit DMA Enable */
1086 /* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/
1110 #define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
1127 #define BUSBUSY 0x0100 /* Bus Busy Indicator */
1159 #define PJSE 0x0001 /* Port J SPI/SPORT Enable */
1163 #define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */
1165 #define PJCE_CAN 0x0002 /* Enable CAN RX/TX */
1169 #define PFDE_UART 0x0000 /* Enable UART0 RX/TX */
1173 #define PFTE_UART 0x0000 /* Enable UART1 RX/TX */
1176 #define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */
1180 #define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */
1184 #define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */
1204 /* entry addresses of the user-callable Boot ROM functions */
1253 #define OTP_DATA0 0xffc03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the …
1254 #define OTP_DATA1 0xffc03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the …
1255 #define OTP_DATA2 0xffc03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the …
1256 #define OTP_DATA3 0xffc0368c /* OTP/Fuse Data (OTP_DATA0-3) accesses the …
1269 #define PWM_SYNCWT 0xffc03724 /* PWM Sync Pluse Width Control */
1296 #define HOST_CNTR_BT_EN 0x80 /* Bus Timeout Enable */
1325 #define HOST_STAT_BTE 0x200 /* Bus Timeout Enabled */