include/asm/def_LPBlackfin.h

2  * Blackfin core register bit & address definitions
4  * Copyright 2005-2008 Analog Devices Inc.
6  * Licensed under the ADI BSD license or GPL-2 (or later).
227 /* Backward-compatibility for typos in prior releases */
232  * Core MMR Register Map
235 /* Data Cache & SRAM Memory  (0xFFE00000 - 0xFFE00404) */
239 #define DCPLB_STATUS       0xFFE00008	/* Data Cache Programmable Look-Aside
243 #define DCPLB_FAULT_ADDR   0xFFE0000C	/* Data Cache Programmable Look-Aside
316 /* Instruction Cache & SRAM Memory  (0xFFE01004 - 0xFFE01404) */
391 /* Event/Interrupt Controller Registers   (0xFFE02000 - 0xFFE02110) */
413 #define IPRIO              0xFFE02110	/* Core Interrupt Priority Register */
415 /* Core Timer Registers     (0xFFE03000 - 0xFFE0300C) */
417 #define TCNTL              0xFFE03000	/* Core Timer Control Register */
418 #define TPERIOD            0xFFE03004	/* Core Timer Period Register */
419 #define TSCALE             0xFFE03008	/* Core Timer Scale Register */
420 #define TCOUNT             0xFFE0300C	/* Core Timer Count Register */
422 /* Debug/MP/Emulation Registers     (0xFFE05000 - 0xFFE05008) */
429 /* Trace Buffer Registers     (0xFFE06000 - 0xFFE06100) */
435 /* Watchpoint Control Registers (0xFFE07000 - 0xFFE07200) */
476 /* Performance Monitor Registers    (0xFFE08000 - 0xFFE08104) */
486  * Core MMR Register Bits
631 #define CPLB_L1_CHBL       0x00001000	/* 0=non-cacheable in L1, 1=cacheable
636 					 * 1=priority for non-replacement
647 					 * write-through writes,
649 					 * write-through writes.
651 #define CPLB_WT            0x00004000	/* 0=write-back, 1=write-through */
676 #define TEST_MB0	   0x00000000	/* Select Mini-Bank 0 */
677 #define TEST_MB1	   0x00010000	/* Select Mini-Bank 1 */
678 #define TEST_MB2	   0x00020000	/* Select Mini-Bank 2 */
679 #define TEST_MB3	   0x00030000	/* Select Mini-Bank 3 */
680 #define TEST_SET(x)	   ((x << 5) & 0x03E0)	/* Set Index 0->31 */