Lines Matching full:only

88 #define S3C2410_UDC_INT_EP4		(1 << 4) /* R/W (clear only) */
89 #define S3C2410_UDC_INT_EP3		(1 << 3) /* R/W (clear only) */
90 #define S3C2410_UDC_INT_EP2		(1 << 2) /* R/W (clear only) */
91 #define S3C2410_UDC_INT_EP1		(1 << 1) /* R/W (clear only) */
92 #define S3C2410_UDC_INT_EP0		(1 << 0) /* R/W (clear only) */
94 #define S3C2410_UDC_USBINT_RESET	(1 << 2) /* R/W (clear only) */
95 #define S3C2410_UDC_USBINT_RESUME	(1 << 1) /* R/W (clear only) */
96 #define S3C2410_UDC_USBINT_SUSPEND	(1 << 0) /* R/W (clear only) */
114 #define S3C2410_UDC_ICSR1_SENTSTL	(1 << 5) /* R/W (clear only) */
116 #define S3C2410_UDC_ICSR1_FFLUSH	(1 << 3) /* W   (set only) */
117 #define S3C2410_UDC_ICSR1_UNDRUN	(1 << 2) /* R/W (clear only) */
118 #define S3C2410_UDC_ICSR1_PKTRDY	(1 << 0) /* R/W (set only) */
126 #define S3C2410_UDC_OCSR1_SENTSTL	(1 << 6) /* R/W (clear only) */
130 #define S3C2410_UDC_OCSR1_OVRRUN	(1 << 2) /* R/W (clear only) */
131 #define S3C2410_UDC_OCSR1_PKTRDY	(1 << 0) /* R/W (clear only) */