include/plat/clock.h

2  * OMAP clock: data structure definitions, function prototypes, shared macros
4  * Copyright (C) 2004-2005, 2008-2010 Nokia Corporation
23  * struct clkops - some clock function pointers
24  * @enable: fn ptr that enables the current clock in hardware
25  * @disable: fn ptr that enables the current clock in hardware
26  * @find_idlest: function returning the IDLEST register for the clock's IP blk
27  * @find_companion: function returning the "companion" clk reg for the clock
28  * @allow_idle: fn ptr that enables autoidle for the current clock in hardware
29  * @deny_idle: fn ptr that disables autoidle for the current clock in hardware
31  * A "companion" clk is an accompanying clock to the one being queried
32  * that must be enabled for the IP module connected to the clock to
35  * block-specific; the hwmod code has been created to handle this, but
75  * struct clksel_rate - register bitfield values corresponding to clk divisors
77  * @div: clock divisor corresponding to @val
83  * @div is the divisor that should be applied to the parent clock's rate
84  * to produce the current clock's rate.
93  * struct clksel - available parent clocks, and a pointer to their divisors
94  * @parent: struct clk * to a possible parent clock
95  * @rates: available divisors for this parent clock
106  * struct dpll_data - DPLL registers and integration data
110  * @clk_bypass: struct clk pointer to the clock's bypass clock input
111  * @clk_ref: struct clk pointer to the clock's reference clock input
116  * @max_multiplier: maximum valid non-bypass multiplier value (actual)
118  * @min_divider: minimum valid non-bypass divider value (actual)
119  * @max_divider: maximum valid non-bypass divider value (actual)
132  * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
139  * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
140  * @last_rounded_n) should be separated from the runtime-fixed fields
141  * and placed into a different structure, so that the runtime-fixed data
142  * can be placed into read-only space.
179  * XXX document the rest of the clock flags here
184  *     should be used.  This is a temporary solution - a better approach
185  *     would be to associate clock type-specific data with the clock,
188 #define ENABLE_REG_32BIT	(1 << 0)	/* Use 32-bit access */
196  * struct clk - OMAP struct clk
197  * @node: list_head connecting this clock into the full clock list
198  * @ops: struct clkops * for this clock
199  * @name: the name of the clock in the hardware (used in hwmod data and debug)
200  * @parent: pointer to this clock's parent struct clk
203  * @rate: current clock rate
204  * @enable_reg: register to write to enable the clock (see @enable_bit)
205  * @recalc: fn ptr that returns the clock's current rate
206  * @set_rate: fn ptr that can change the clock's current rate
207  * @round_rate: fn ptr that can round the clock's current rate
208  * @init: fn ptr to do clock-specific initialization
209  * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
210  * @usecount: number of users that have requested this clock to be enabled
211  * @fixed_div: when > 0, this clock's rate is its parent's rate / @fixed_div
215  * @clksel: for clksel clks, pointer to struct clksel for this clock
216  * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
217  * @clkdm_name: clockdomain name that this clock is contained in
223  * clock code converted to use clksel.
229  * incremented by the clock code when clk_enable() is called on child
230  * clocks and decremented by the clock code when clk_disable() is
236  * @children and @sibling are used to optimize parent-to-child clock
237  * tree traversals.  (child-to-parent traversals use @parent.)
239  * XXX The notion of the clock's current rate probably needs to be
240  * separated from the clock's target rate.