arm/mm/proc-xsc3.S

2  * linux/arch/arm/mm/proc-xsc3.S
14  * MMU functions for the Intel XScale3 Core (XSC3).  The XSC3 core is
15  * an extension to Intel's original XScale core that adds the following
18  * - ARMv6 Supersections
19  * - Low Locality Reference pages (replaces mini-cache)
20  * - 36-bit addressing
21  * - L2 cache
22  * - Cache coherency if chipset supports it
32 #include <asm/pgtable-hwdef.h>
35 #include "proc-macros.S"
187  *	- start - start address (may not be aligned)
188  *	- end	- end address (exclusive, may not be aligned)
189  *	- vma	- vma_area_struct describing address space
214  *	region described by start.  If you have non-snooping
217  *	- start  - virtual start address
218  *	- end	 - virtual end address
220  *	Note: single I-cache line invalidation isn't used here since
221  *	it also trashes the mini I-cache used by JTAG debuggers.
226 	bic	r0, r0, #CACHELINESIZE - 1
243  *	- addr	- kernel address
244  *	- size	- region size
266  *	- start  - virtual start address
267  *	- end	 - virtual end address
270 	tst	r0, #CACHELINESIZE - 1
271 	bic	r0, r0, #CACHELINESIZE - 1
273 	tst	r1, #CACHELINESIZE - 1
287  *	- start  - virtual start address
288  *	- end	 - virtual end address
291 	bic	r0, r0, #CACHELINESIZE - 1
304  *	- start  - virtual start address
305  *	- end	 - virtual end address
308 	bic	r0, r0, #CACHELINESIZE - 1
318  *	- start	- kernel virtual start address
319  *	- size	- size of region
320  *	- dir	- DMA direction
332  *	- start	- kernel virtual start address
333  *	- size	- size of region
334  *	- dir	- DMA direction
340 	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
415 	stmfd	sp!, {r4 - r9, lr}
423 	stmia	r0, {r4 - r9}		@ store cp regs
424 	ldmia	sp!, {r4 - r9, pc}
428 	ldmia	r0, {r4 - r9}		@ load cp regs
482 	.size	__xsc3_setup, . - __xsc3_setup
490 	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
497 	string	cpu_xsc3_name, "XScale-V3 based processor"
525 	.size	__\name\()_proc_info, . - __\name\()_proc_info