Lines Matching full:read
80 * Controller (UDC) Control Register (read/write).
82 * Controller (UDC) Address Register (read/write).
85 * (read/write).
88 * (read/write).
91 * (read/write).
94 * (output, read/write).
97 * (input, read/write).
100 * (read/write).
103 * (read).
105 * Controller (UDC) Data Register (read/write).
107 * Controller (UDC) Status Register (read/write).
123 #define UDCCR_UDA 0x00000002 /* UDC Active (read) */
150 #define UDCCS0_OPR 0x00000001 /* Output Packet Ready (read) */
155 #define UDCCS0_SE 0x00000020 /* Setup End (read) */
161 /* Service request (read) */
163 #define UDCCS1_RPE 0x00000004 /* Receive Packet Error (read) */
166 #define UDCCS1_RNE 0x00000020 /* Receive FIFO Not Empty (read) */
169 /* Service request (read) */
171 #define UDCCS2_TPE 0x00000004 /* Transmit Packet Error (read) */
196 * (read/write).
199 * (read/write).
202 * (read/write).
205 * (read/write).
208 * (read/write).
211 * (read/write).
213 * Receiver/Transmitter (UART) Status Register 1 (read).
217 * (read/write).
220 * (read/write).
223 * (read/write).
226 * (read/write).
229 * (read/write).
232 * (read/write).
235 * (read/write).
237 * Receiver/Transmitter (UART) Status Register 1 (read).
241 * (read/write).
244 * (read/write).
247 * (read/write).
250 * (read/write).
253 * (read/write).
256 * (read/write).
258 * Receiver/Transmitter (UART) Status Register 1 (read).
379 #define UTDR_PRE 0x00000100 /* receive PaRity Error (read) */
380 #define UTDR_FRE 0x00000200 /* receive FRaming Error (read) */
381 #define UTDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */
385 /* Service request (read) */
387 /* more Service request (read) */
391 #define UTSR0_EIF 0x00000020 /* Error In FIFO (read) */
393 #define UTSR1_TBY 0x00000001 /* Transmitter BusY (read) */
394 #define UTSR1_RNE 0x00000002 /* Receive FIFO Not Empty (read) */
395 #define UTSR1_TNF 0x00000004 /* Transmit FIFO Not Full (read) */
396 #define UTSR1_PRE 0x00000008 /* receive PaRity Error (read) */
397 #define UTSR1_FRE 0x00000010 /* receive FRaming Error (read) */
398 #define UTSR1_ROR 0x00000020 /* Receive FIFO Over-Run (read) */
406 * Control Register 0 (read/write).
408 * Control Register 1 (read/write).
410 * Control Register 2 (read/write).
412 * Control Register 3 (read/write).
414 * Control Register 4 (read/write).
416 * Data Register (read/write).
418 * Status Register 0 (read/write).
420 * Status Register 1 (read/write).
498 #define SDDR_EOF 0x00000100 /* receive End-Of-Frame (read) */
499 #define SDDR_CRE 0x00000200 /* receive CRC Error (read) */
500 #define SDDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */
503 #define SDSR0_EIF 0x00000001 /* Error In FIFO (read) */
507 /* Service request (read) */
509 /* more Service request (read) */
511 #define SDSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */
512 #define SDSR1_TBY 0x00000002 /* Transmitter BusY (read) */
513 #define SDSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */
514 #define SDSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */
516 #define SDSR1_EOF 0x00000020 /* receive End-Of-Frame (read) */
517 #define SDSR1_CRE 0x00000040 /* receive CRC Error (read) */
518 #define SDSR1_ROR 0x00000080 /* Receive FIFO Over-Run (read) */
526 * controller (HSSP) Control Register 0 (read/write).
528 * controller (HSSP) Control Register 1 (read/write).
530 * controller (HSSP) Data Register (read/write).
532 * controller (HSSP) Status Register 0 (read/write).
534 * controller (HSSP) Status Register 1 (read).
536 * controller (HSSP) Control Register 2 (read/write).
568 #define HSDR_EOF 0x00000100 /* receive End-Of-Frame (read) */
569 #define HSDR_CRE 0x00000200 /* receive CRC Error (read) */
570 #define HSDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */
573 #define HSSR0_EIF 0x00000001 /* Error In FIFO (read) */
577 /* Service request (read) */
579 /* more Service request (read) */
582 #define HSSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */
583 #define HSSR1_TBY 0x00000002 /* Transmitter BusY (read) */
584 #define HSSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */
585 #define HSSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */
586 #define HSSR1_EOF 0x00000010 /* receive End-Of-Frame (read) */
587 #define HSSR1_CRE 0x00000020 /* receive CRC Error (read) */
588 #define HSSR1_ROR 0x00000040 /* Receive FIFO Over-Run (read) */
607 * Control Register 0 (read/write).
609 * Data Register 0 (audio, read/write).
611 * Data Register 1 (telecom, read/write).
613 * Data Register 2 (CODEC registers, read/write).
615 * Status Register (read/write).
617 * Control Register 1 (read/write).
692 #define MCDR2_RW 0x00010000 /* reg. Read/Write (transmit) */
693 #define MCDR2_Rd (MCDR2_RW*0) /* reg. Read */
698 /* or less Service request (read) */
700 /* more Service request (read) */
702 /* or less Service request (read) */
704 /* or more Service request (read) */
710 /* (read) */
712 /* (read) */
714 /* (read) */
716 /* (read) */
718 /* (read) */
719 #define MCSR_CRC 0x00002000 /* CODEC register Read Completed */
720 /* (read) */
721 #define MCSR_ACE 0x00004000 /* Audio CODEC Enabled (read) */
722 #define MCSR_TCE 0x00008000 /* Telecom CODEC Enabled (read) */
736 * Register 0 (read/write).
738 * Register 1 (read/write).
742 * Register (read/write).
744 * Register (read/write).
801 #define SSSR_TNF 0x00000002 /* Transmit FIFO Not Full (read) */
802 #define SSSR_RNE 0x00000004 /* Receive FIFO Not Empty (read) */
803 #define SSSR_BSY 0x00000008 /* SSP BuSY (read) */
805 /* Service request (read) */
807 /* Service request (read) */
816 * (read/write).
818 * (read/write).
820 * (read/write).
822 * (read/write).
824 * (read/write).
826 * (read/write).
828 * (read/write).
830 * (read/write).
864 * RTAR Real-Time Clock (RTC) Alarm Register (read/write).
865 * RCNR Real-Time Clock (RTC) CouNt Register (read/write).
866 * RTTR Real-Time Clock (RTC) Trim Register (read/write).
867 * RTSR Real-Time Clock (RTC) Status Register (read/write).
898 * PMCR Power Manager (PM) Control Register (read/write).
899 * PSSR Power Manager (PM) Sleep Status Register (read/write).
900 * PSPR Power Manager (PM) Scratch-Pad Register (read/write).
902 * (read/write).
904 * (read/write).
906 * Configuration Register (read/write).
908 * Sleep state Register (read/write, see GPIO pins).
909 * POSR Power Manager (PM) Oscillator Status Register (read).
1054 * (read/write).
1055 * RCSR Reset Controller (RC) Status Register (read/write).
1073 * TUCR Test Unit Control Register (read/write).
1118 * Register (read).
1120 * Register (read/write).
1126 * detect Register (read/write).
1128 * detect Register (read/write).
1130 * status Register (read/write).
1132 * Function Register (read/write).
1227 * Pending register (read).
1228 * ICMR Interrupt Controller (IC) Mask Register (read/write).
1229 * ICLR Interrupt Controller (IC) Level Register (read/write).
1231 * (read/write).
1235 * (FIQ) Pending register (read).
1236 * ICPR Interrupt Controller (IC) Pending Register (read).
1305 * Register (read/write).
1307 * (read/write).
1309 * Register (read/write).
1311 * Direction Register (read/write).
1313 * (read).
1384 * CoNFiGuration register (read/write).
1387 * (read/write).
1390 * (read/write).
1393 * (read/write).
1467 * (read/write).
1469 * (read/write).
1499 #define MSC_RDF Fld (5, 3) /* ROM/static memory read Delay */
1501 #define MSC_1stRdAcc(Tcpu) /* 1st Read Access time (burst */ \
1506 #define MSC_RdAcc(Tcpu) /* Read Access time (non-burst */ \
1511 #define MSC_RDN Fld (5, 8) /* ROM/static memory read Delay */
1513 #define MSC_NxtRdAcc(Tcpu) /* Next Read Access time (burst */ \
1537 * Configuration Register (read/write).
1596 * channel 0 (read/write).
1598 * Register channel 0 (read/write).
1600 * register A channel 0 (read/write).
1602 * register A channel 0 (read/write).
1604 * register B channel 0 (read/write).
1606 * register B channel 0 (read/write).
1609 * channel 1 (read/write).
1611 * Register channel 1 (read/write).
1613 * register A channel 1 (read/write).
1615 * register A channel 1 (read/write).
1617 * register B channel 1 (read/write).
1619 * register B channel 1 (read/write).
1622 * channel 2 (read/write).
1624 * Register channel 2 (read/write).
1626 * register A channel 2 (read/write).
1628 * register A channel 2 (read/write).
1630 * register B channel 2 (read/write).
1632 * register B channel 2 (read/write).
1635 * channel 3 (read/write).
1637 * Register channel 3 (read/write).
1639 * register A channel 3 (read/write).
1641 * register A channel 3 (read/write).
1643 * register B channel 3 (read/write).
1645 * register B channel 3 (read/write).
1648 * channel 4 (read/write).
1650 * Register channel 4 (read/write).
1652 * register A channel 4 (read/write).
1654 * register A channel 4 (read/write).
1656 * register B channel 4 (read/write).
1658 * register B channel 4 (read/write).
1661 * channel 5 (read/write).
1663 * Register channel 5 (read/write).
1665 * register A channel 5 (read/write).
1667 * register A channel 5 (read/write).
1669 * register B channel 5 (read/write).
1671 * register B channel 5 (read/write).
1679 …fine RdDCSR(Nb) __REG(0xB000000C + (Nb)*DMASp) /* Read DMA Control & Status Reg. channel [0..5] (…
1685 #define DDAR_RW 0x00000001 /* device data Read/Write */
1688 #define DDAR_DevRd (DDAR_RW*1) /* Device data Read */
1743 #define DDAR_Ser0UDCRd /* Ser. port 0 UDC Read */ \
1749 #define DDAR_Ser1UARTRd /* Ser. port 1 UART Read */ \
1755 #define DDAR_Ser1SDLCRd /* Ser. port 1 SDLC Read */ \
1761 #define DDAR_Ser2UARTRd /* Ser. port 2 UART Read */ \
1767 #define DDAR_Ser2HSSPRd /* Ser. port 2 HSSP Read */ \
1773 #define DDAR_Ser3UARTRd /* Ser. port 3 UART Read */ \
1779 #define DDAR_Ser4MCP0Rd /* Ser. port 4 MCP 0 Read (audio) */ \
1786 #define DDAR_Ser4MCP1Rd /* Ser. port 4 MCP 1 Read */ \
1793 #define DDAR_Ser4SSPRd /* Ser. port 4 SSP Read (16 bits) */ \
1818 * (read/write).
1823 * (read/write).
1824 * [Bit LDD can be only read in versions 1.0 (rev. = 1)
1826 * read and written (cleared) in versions 2.0 (rev. = 8)
1829 * (DMA) Base Address Register channel 1 (read/write).
1831 * (DMA) Current Address Register channel 1 (read).
1833 * (DMA) Base Address Register channel 2 (read/write).
1835 * (DMA) Current Address Register channel 2 (read).
1837 * (read/write).
1840 * StrongARM SA-1100, it can be written and read in
1843 * (read/write).
1846 * StrongARM SA-1100, it can be written and read in
1849 * (read/write).
1852 * StrongARM SA-1100, it can be written and read in
1950 #define LCSR_BAU 0x00000002 /* Base Address Update (read) */