Lines Matching defs:Nb
56 #define _PCMCIA(Nb) /* PCMCIA [0..1] */ \ argument
58 #define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */ argument
59 #define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \ argument
61 #define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \ argument
266 #define _UTCR0(Nb) __REG(0x80010000 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 0 [1..3] */ argument
267 #define _UTCR1(Nb) __REG(0x80010004 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 1 [1..3] */ argument
268 #define _UTCR2(Nb) __REG(0x80010008 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 2 [1..3] */ argument
269 #define _UTCR3(Nb) __REG(0x8001000C + ((Nb) - 1)*0x00020000) /* UART Control Reg. 3 [1..3] */ argument
270 #define _UTCR4(Nb) __REG(0x80010010 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 4 [2] */ argument
271 #define _UTDR(Nb) __REG(0x80010014 + ((Nb) - 1)*0x00020000) /* UART Data Reg. [1..3] */ argument
272 #define _UTSR0(Nb) __REG(0x8001001C + ((Nb) - 1)*0x00020000) /* UART Status Reg. 0 [1..3] */ argument
273 #define _UTSR1(Nb) __REG(0x80010020 + ((Nb) - 1)*0x00020000) /* UART Status Reg. 1 [1..3] */ argument
842 #define OSSR_M(Nb) /* Match detected [0..3] */ \ argument
852 #define OIER_E(Nb) /* match interrupt Enable [0..3] */ \ argument
935 #define PWER_GPIO(Nb) GPIO_GPIO (Nb) /* GPIO [0..27] wake-up enable */ argument
1150 #define GPIO_GPIO(Nb) /* GPIO [0..27] */ \ argument
1181 #define GPIO_LDD(Nb) /* LCD Data [8..15] (O) */ \ argument
1250 #define IC_GPIO(Nb) /* GPIO [0..10] */ \ argument
1272 #define IC_DMA(Nb) /* DMA controller channel [0..5] */ \ argument
1280 #define IC_OST(Nb) /* OS Timer match [0..3] */ \ argument
1322 #define PPC_LDD(Nb) /* LCD Data [0..7] */ \ argument
1407 #define MDCNFG_DE(Nb) /* DRAM Enable bank [0..3] */ \ argument
1480 #define MSC_Bnk(Nb) /* static memory Bank [0..3] */ \ argument
1548 #define MECR_PCMCIA(Nb) /* PCMCIA [0..1] */ \ argument
1676 #define DDAR(Nb) __REG(0xB0000000 + (Nb)*DMASp) /* DMA Device Address Reg. channel [0..5] */ argument
1677 #define SetDCSR(Nb) __REG(0xB0000004 + (Nb)*DMASp) /* Set DMA Control & Status Reg. channel [0..5]… argument
1678 #define ClrDCSR(Nb) __REG(0xB0000008 + (Nb)*DMASp) /* Clear DMA Control & Status Reg. channel [0..… argument
1679 #define RdDCSR(Nb) __REG(0xB000000C + (Nb)*DMASp) /* Read DMA Control & Status Reg. channel [0..5]… argument
1680 #define DBSA(Nb) __REG(0xB0000010 + (Nb)*DMASp) /* DMA Buffer Start address reg. A channel [0..5] … argument
1681 #define DBTA(Nb) __REG(0xB0000014 + (Nb)*DMASp) /* DMA Buffer Transfer count reg. A channel [0..5]… argument
1682 #define DBSB(Nb) __REG(0xB0000018 + (Nb)*DMASp) /* DMA Buffer Start address reg. B channel [0..5] … argument
1683 #define DBTB(Nb) __REG(0xB000001C + (Nb)*DMASp) /* DMA Buffer Transfer count reg. B channel [0..5]… argument