340 #define UTCR1_BdRtDiv(Div)      	/*  Baud Rate Divisor [16..65536]  */ \  argument
343 #define UTCR2_BdRtDiv(Div)      	/*  Baud Rate Divisor [16..65536]  */ \  argument
348 #define UTCR1_CeilBdRtDiv(Div)  	/*  Ceil. of BdRtDiv [16..65536]   */ \  argument
351 #define UTCR2_CeilBdRtDiv(Div)  	/*  Ceil. of BdRtDiv [16..65536]   */ \  argument
479 #define SDCR3_BdRtDiv(Div)      	/*  Baud Rate Divisor [16..65536]  */ \  argument
482 #define SDCR4_BdRtDiv(Div)      	/*  Baud Rate Divisor [16..65536]  */ \  argument
487 #define SDCR3_CeilBdRtDiv(Div)  	/*  Ceil. of BdRtDiv [16..65536]   */ \  argument
490 #define SDCR4_CeilBdRtDiv(Div)  	/*  Ceil. of BdRtDiv [16..65536]   */ \  argument
640 #define MCCR0_AudSmpDiv(Div)    	/*  Audio Sampling rate Divisor    */ \  argument
645 #define MCCR0_CeilAudSmpDiv(Div)	/*  Ceil. of AudSmpDiv [192..4064] */ \  argument
653 #define MCCR0_TcmSmpDiv(Div)    	/*  Telecom Sampling rate Divisor  */ \  argument
658 #define MCCR0_CeilTcmSmpDiv(Div)	/*  Ceil. of TcmSmpDiv [512..4064] */ \  argument
680 #define MCCR0_ExtClkDiv(Div)    	/*  External Clock Divisor [1..4]  */ \  argument
773 #define SSCR0_SerClkDiv(Div)    	/*  Serial Clock Divisor [2..512]  */ \  argument
777 #define SSCR0_CeilSerClkDiv(Div)	/*  Ceil. of SerClkDiv [2..512]    */ \  argument
2012 #define LCCR3_PixClkDiv(Div)    	/*  Pixel Clock Divisor [6..514]   */ \  argument
2016 #define LCCR3_CeilPixClkDiv(Div)	/*  Ceil. of PixClkDiv [6..514]    */ \  argument
2022 #define LCCR3_ACBsDiv(Div)      	/*  AC Bias clock Divisor [2..512] */ \  argument
2026 #define LCCR3_CeilACBsDiv(Div)  	/*  Ceil. of ACBsDiv [2..512]      */ \  argument