Lines Matching full:3
31 #define S3C2416_SELECT_DSC3 (3 << 30)
39 #define S3C2416_DSC0_CF_21mA (3 << 28)
40 #define S3C2416_DSC0_CF_MASK (3 << 28)
46 #define S3C2416_DSC0_nRBE_21mA (3 << 26)
47 #define S3C2416_DSC0_nRBE_MASK (3 << 26)
53 #define S3C2416_DSC0_nROE_21mA (3 << 24)
54 #define S3C2416_DSC0_nROE_MASK (3 << 24)
74 #define S3C2440_DSC0_ADDR_6mA (3<<8)
75 #define S3C2440_DSC0_ADDR_MASK (3<<8)
82 #define S3C2440_DSC0_DATA3_6mA (3<<6)
83 #define S3C2440_DSC0_DATA3_MASK (3<<6)
90 #define S3C2440_DSC0_DATA2_6mA (3<<4)
91 #define S3C2440_DSC0_DATA2_MASK (3<<4)
98 #define S3C2440_DSC0_DATA1_6mA (3<<2)
99 #define S3C2440_DSC0_DATA1_MASK (3<<2)
106 #define S3C2440_DSC0_DATA0_6mA (3<<0)
107 #define S3C2440_DSC0_DATA0_MASK (3<<0)
113 #define S3C2440_DSC1_SCK1_6mA (3<<28)
114 #define S3C2440_DSC1_SCK1_MASK (3<<28)
120 #define S3C2440_DSC1_SCK0_6mA (3<<26)
121 #define S3C2440_DSC1_SCK0_MASK (3<<26)
127 #define S3C2440_DSC1_SCKE_4mA (3<<24)
128 #define S3C2440_DSC1_SCKE_MASK (3<<24)
135 #define S3C2440_DSC1_SDR_4mA (3<<22)
136 #define S3C2440_DSC1_SDR_MASK (3<<22)
143 #define S3C2440_DSC1_NFC_4mA (3<<20)
144 #define S3C2440_DSC1_NFC_MASK (3<<20)
146 /* nBE[0..3] */
151 #define S3C2440_DSC1_nBE_4mA (3<<18)
152 #define S3C2440_DSC1_nBE_MASK (3<<18)
158 #define S3C2440_DSC1_WOE_4mA (3<<16)
159 #define S3C2440_DSC1_WOE_MASK (3<<16)
165 #define S3C2440_DSC1_CS7_4mA (3<<14)
166 #define S3C2440_DSC1_CS7_MASK (3<<14)
172 #define S3C2440_DSC1_CS6_4mA (3<<12)
173 #define S3C2440_DSC1_CS6_MASK (3<<12)
179 #define S3C2440_DSC1_CS5_4mA (3<<10)
180 #define S3C2440_DSC1_CS5_MASK (3<<10)
186 #define S3C2440_DSC1_CS4_4mA (3<<8)
187 #define S3C2440_DSC1_CS4_MASK (3<<8)
193 #define S3C2440_DSC1_CS3_4mA (3<<6)
194 #define S3C2440_DSC1_CS3_MASK (3<<6)
200 #define S3C2440_DSC1_CS2_4mA (3<<4)
201 #define S3C2440_DSC1_CS2_MASK (3<<4)
207 #define S3C2440_DSC1_CS1_4mA (3<<2)
208 #define S3C2440_DSC1_CS1_MASK (3<<2)
214 #define S3C2440_DSC1_CS0_4mA (3<<0)
215 #define S3C2440_DSC1_CS0_MASK (3<<0)