Lines Matching full:32
49 #define INT_AXI_EBI1_SC (32 + 0)
50 #define INT_IMEM_ERR (32 + 1)
51 #define INT_AXI_EBI0_SC (32 + 2)
52 #define INT_PBUS_SC_IRQC (32 + 3)
53 #define INT_PERPH_BUS_BPM (32 + 4)
54 #define INT_CC_TEMP_SENSE (32 + 5)
55 #define INT_UXMC_EBI0 (32 + 6)
56 #define INT_UXMC_EBI1 (32 + 7)
57 #define INT_EBI2_OP_DONE (32 + 8)
58 #define INT_EBI2_WR_ER_DONE (32 + 9)
59 #define INT_TCSR_SPSS_CE (32 + 10)
60 #define INT_EMDH (32 + 11)
61 #define INT_PMDH (32 + 12)
62 #define INT_MDC (32 + 13)
63 #define INT_MIDI_TO_SUPSS (32 + 14)
64 #define INT_LPA_2 (32 + 15)
65 #define INT_GPIO_GROUP1_SECURE (32 + 16)
66 #define INT_GPIO_GROUP2_SECURE (32 + 17)
67 #define INT_GPIO_GROUP1 (32 + 18)
68 #define INT_GPIO_GROUP2 (32 + 19)
69 #define INT_MPRPH_SOFTRESET (32 + 20)
70 #define INT_PWB_I2C (32 + 21)
71 #define INT_PWB_I2C_2 (32 + 22)
72 #define INT_TSSC_SAMPLE (32 + 23)
73 #define INT_TSSC_PENUP (32 + 24)
74 #define INT_TCHSCRN_SSBI (32 + 25)
75 #define INT_FM_RDS (32 + 26)
76 #define INT_KEYSENSE (32 + 27)
77 #define INT_USB_OTG_HS (32 + 28)
78 #define INT_USB_OTG_HS2 (32 + 29)
79 #define INT_USB_OTG_HS3 (32 + 30)
80 #define INT_CSI (32 + 31)