Lines Matching full:if
36 if (clk->parent) in __clk_enable()
38 if (clk->usecount++ == 0 && (clk->flags & CLK_PSC)) in __clk_enable()
45 if (WARN_ON(clk->usecount == 0)) in __clk_disable()
47 if (--clk->usecount == 0 && !(clk->flags & CLK_PLL) && in __clk_disable()
51 if (clk->parent) in __clk_disable()
59 if (clk == NULL || IS_ERR(clk)) in clk_enable()
74 if (clk == NULL || IS_ERR(clk)) in clk_disable()
85 if (clk == NULL || IS_ERR(clk)) in clk_get_rate()
94 if (clk == NULL || IS_ERR(clk)) in clk_round_rate()
97 if (clk->round_rate) in clk_round_rate()
110 if (clk->recalc) in propagate_rate()
121 if (clk == NULL || IS_ERR(clk)) in clk_set_rate()
124 if (clk->set_rate) in clk_set_rate()
128 if (ret == 0) { in clk_set_rate()
129 if (clk->recalc) in clk_set_rate()
143 if (clk == NULL || IS_ERR(clk)) in clk_set_parent()
147 if (WARN_ON(clk->usecount)) in clk_set_parent()
157 if (clk->recalc) in clk_set_parent()
168 if (clk == NULL || IS_ERR(clk)) in clk_register()
171 if (WARN(clk->parent && !clk->parent->rate, in clk_register()
180 if (clk->parent) in clk_register()
184 /* If rate is already set, use it */ in clk_register()
185 if (clk->rate) in clk_register()
188 /* Else, see if there is a way to calculate it */ in clk_register()
189 if (clk->recalc) in clk_register()
193 else if (clk->parent) in clk_register()
202 if (clk == NULL || IS_ERR(clk)) in clk_unregister()
222 if (ck->usecount > 0) in clk_disable_unused()
224 if (!(ck->flags & CLK_PSC)) in clk_disable_unused()
227 /* ignore if in Disabled or SwRstDisable states */ in clk_disable_unused()
228 if (!davinci_psc_is_clk_active(ck->gpsc, ck->lpsc)) in clk_disable_unused()
249 /* If this is the PLL base clock, no more calculations needed */ in clk_sysclk_recalc()
250 if (clk->pll_data) in clk_sysclk_recalc()
253 if (WARN_ON(!clk->parent)) in clk_sysclk_recalc()
259 if (WARN_ON(!clk->parent->pll_data)) in clk_sysclk_recalc()
264 /* If pre-PLL, source clock is before the multiplier and divider(s) */ in clk_sysclk_recalc()
265 if (clk->flags & PRE_PLL) in clk_sysclk_recalc()
268 if (!clk->div_reg) in clk_sysclk_recalc()
272 if (v & PLLDIV_EN) { in clk_sysclk_recalc()
274 if (plldiv) in clk_sysclk_recalc()
288 /* If this is the PLL base clock, wrong function to call */ in davinci_set_sysclk_rate()
289 if (clk->pll_data) in davinci_set_sysclk_rate()
293 if (WARN_ON(!clk->parent)) in davinci_set_sysclk_rate()
297 if (WARN_ON(!clk->parent->pll_data)) in davinci_set_sysclk_rate()
301 if (WARN_ON(!clk->div_reg)) in davinci_set_sysclk_rate()
308 /* If pre-PLL, source clock is before the multiplier and divider(s) */ in davinci_set_sysclk_rate()
309 if (clk->flags & PRE_PLL) in davinci_set_sysclk_rate()
312 if (input > rate) { in davinci_set_sysclk_rate()
315 * only if maximum rate supported by hardware on this sysclk in davinci_set_sysclk_rate()
318 if (clk->maxrate) { in davinci_set_sysclk_rate()
320 if (input / ratio > clk->maxrate) in davinci_set_sysclk_rate()
324 if (ratio == 0) in davinci_set_sysclk_rate()
330 if (ratio > pll->div_ratio_mask) in davinci_set_sysclk_rate()
356 if (WARN_ON(!clk->parent)) in clk_leafclk_recalc()
378 if (ctrl & PLLCTL_PLLEN) { in clk_pllclk_recalc()
381 if (cpu_is_davinci_dm365()) in clk_pllclk_recalc()
388 if (pll->flags & PLL_HAS_PREDIV) { in clk_pllclk_recalc()
390 if (prediv & PLLDIV_EN) in clk_pllclk_recalc()
397 if (cpu_is_davinci_dm355() && pll->num == 1) in clk_pllclk_recalc()
400 if (pll->flags & PLL_HAS_POSTDIV) { in clk_pllclk_recalc()
402 if (postdiv & PLLDIV_EN) in clk_pllclk_recalc()
408 if (!bypass) { in clk_pllclk_recalc()
416 if (bypass) in clk_pllclk_recalc()
418 if (prediv > 1) in clk_pllclk_recalc()
420 if (mult > 1) in clk_pllclk_recalc()
422 if (postdiv > 1) in clk_pllclk_recalc()
446 if (pll->base == NULL) in davinci_set_pllrate()
454 if (prediv) { in davinci_set_pllrate()
460 if (postdiv) in davinci_set_pllrate()
462 if (mult) in davinci_set_pllrate()
480 if (pll->flags & PLL_HAS_PREDIV) in davinci_set_pllrate()
485 if (pll->flags & PLL_HAS_POSTDIV) in davinci_set_pllrate()
526 if (IS_ERR(refclk)) { in davinci_set_refclk_rate()
547 if (!clk->recalc) { in davinci_clk_init()
549 /* Check if clock is a PLL */ in davinci_clk_init()
550 if (clk->pll_data) in davinci_clk_init()
553 /* Else, if it is a PLL-derived clock */ in davinci_clk_init()
554 else if (clk->flags & CLK_PLL) in davinci_clk_init()
558 else if (clk->parent) in davinci_clk_init()
562 if (clk->pll_data) { in davinci_clk_init()
565 if (!pll->div_ratio_mask) in davinci_clk_init()
568 if (pll->phys_base && !pll->base) { in davinci_clk_init()
574 if (clk->recalc) in davinci_clk_init()
577 if (clk->lpsc) in davinci_clk_init()
584 if (clk->flags & ALWAYS_ENABLED) in davinci_clk_init()
610 if (parent->flags & CLK_PLL) in dump_clock()
612 else if (parent->flags & CLK_PSC) in dump_clock()
643 if (!clk->parent) in davinci_ck_show()