Lines Matching +full:spi +full:- +full:mux
2 * Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
42 uint32_t SPIClock; /* PLL1 Channel 9 for SPI master Clock */
63 uint32_t PLLPreDivider; /* PLL pre-divider control register (PLL1) */
79 uint32_t PLLPreDivider2; /* PLL pre-divider control register (PLL2) */
101 uint32_t LcdPifMode; /* LCD/PIF Pin Sharing MUX Mode */
112 uint32_t GpioSR_0_7; /* Slew rate for GPIO 0 - 7 */
113 uint32_t GpioSR_8_15; /* Slew rate for GPIO 8 - 15 */
114 uint32_t GpioSR_16_23; /* Slew rate for GPIO 16 - 23 */
115 uint32_t GpioSR_24_31; /* Slew rate for GPIO 24 - 31 */
116 uint32_t GpioSR_32_39; /* Slew rate for GPIO 32 - 39 */
117 uint32_t GpioSR_40_47; /* Slew rate for GPIO 40 - 47 */
118 uint32_t GpioSR_48_55; /* Slew rate for GPIO 48 - 55 */
119 uint32_t GpioSR_56_63; /* Slew rate for GPIO 56 - 63 */
120 uint32_t MiscSR_0_7; /* Slew rate for MISC 0 - 7 */
121 uint32_t MiscSR_8_15; /* Slew rate for MISC 8 - 15 */
123 uint32_t GpioPull_0_15; /* Pull up registers for GPIO 0 - 15 */
124 uint32_t GpioPull_16_31; /* Pull up registers for GPIO 16 - 31 */
125 uint32_t GpioPull_32_47; /* Pull up registers for GPIO 32 - 47 */
126 uint32_t GpioPull_48_63; /* Pull up registers for GPIO 48 - 63 */
127 uint32_t MiscPull_0_15; /* Pull up registers for MISC 0 - 15 */
129 uint32_t GpioInput_0_31; /* Input type for GPIO 0 - 31 */
130 uint32_t GpioInput_32_63; /* Input type for GPIO 32 - 63 */
131 uint32_t MiscInput_0_15; /* Input type for MISC 0 - 16 */
151 #define chipcHw_REG_PLL_CONFIG_VCO_800_1600 0x00000000 /* VCO range 800-1600 MHz */
152 #define chipcHw_REG_PLL_CONFIG_VCO_1601_3200 0x00000080 /* VCO range 1601-3200 MHz */
169 00000000 = divide-by-256
170 00000001 = divide-by-1
171 00000010 = divide-by-2
172 00000011 = divide-by-3
173 00000100 = divide-by-4
174 00000101 = divide-by-5
175 00000110 = divide-by-6
178 11111011 = divide-by-251
179 11111100 = divide-by-252
180 11111101 = divide-by-253
181 11111110 = divide-by-254
184 #define chipcHw_REG_DIV_CLOCK_SOURCE_OTHER 0x00040000 /* NON-PLL clock source select */
185 #define chipcHw_REG_DIV_CLOCK_BYPASS_SELECT 0x00020000 /* NON-PLL clock bypass enable */
186 #define chipcHw_REG_DIV_CLOCK_OUTPUT_ENABLE 0x00010000 /* NON-PLL clock output enable */
187 #define chipcHw_REG_DIV_CLOCK_DIV_MASK 0x000000FF /* NON-PLL clock post-divide mas…
188 #define chipcHw_REG_DIV_CLOCK_DIV_256 0x00000000 /* NON-PLL clock post-divide by …
196 #define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER 0x00000000 /* Integer-N Mode */
197 #define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASH_UNIT 0x00100000 /* MASH Sigma-Delta Modulator Un…
198 #define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MFB_UNIT 0x00200000 /* MFB Sigma-Delta Modulator Uni…
199 #define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASH_1_8 0x00300000 /* MASH Sigma-Delta Modulator 1/…
200 #define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MFB_1_8 0x00400000 /* MFB Sigma-Delta Modulator 1/8…
254 #define chipcHw_STRAPS_SPIS 0x01000000 /* SPI Slave */
257 #define chipcHw_REG_SW_STRAPS ((pChipcHw->PinStraps & 0x0000FC00) >> 10)
266 #define chipcHw_REG_GPIO_MUX_KEYPAD 0x00000001 /* GPIO mux for Keypad */
267 #define chipcHw_REG_GPIO_MUX_I2CH 0x00000002 /* GPIO mux for I2CH */
268 #define chipcHw_REG_GPIO_MUX_SPI 0x00000003 /* GPIO mux for SPI */
269 #define chipcHw_REG_GPIO_MUX_UART 0x00000004 /* GPIO mux for UART */
270 #define chipcHw_REG_GPIO_MUX_LEDMTXP 0x00000005 /* GPIO mux for LEDMTXP */
271 #define chipcHw_REG_GPIO_MUX_LEDMTXS 0x00000006 /* GPIO mux for LEDMTXS */
272 #define chipcHw_REG_GPIO_MUX_SDIO0 0x00000007 /* GPIO mux for SDIO0 */
273 #define chipcHw_REG_GPIO_MUX_SDIO1 0x00000008 /* GPIO mux for SDIO1 */
274 #define chipcHw_REG_GPIO_MUX_PCM 0x00000009 /* GPIO mux for PCM */
275 #define chipcHw_REG_GPIO_MUX_I2S 0x0000000A /* GPIO mux for I2S */
276 #define chipcHw_REG_GPIO_MUX_ETM 0x0000000B /* GPIO mux for ETM */
277 #define chipcHw_REG_GPIO_MUX_DEBUG 0x0000000C /* GPIO mux for DEBUG */
278 #define chipcHw_REG_GPIO_MUX_MISC 0x0000000D /* GPIO mux for MISC */
279 #define chipcHw_REG_GPIO_MUX_GPIO 0x00000000 /* GPIO mux for GPIO */
280 #define chipcHw_REG_GPIO_MUX(pin) (&pChipcHw->GpioMux_0_7 + ((pin) >> 3))
287 …pin) (((pin) > 42) ? (&pChipcHw->GpioSR_0_7 + (((pin) + 2) >> 3)) : (&pChipcH…
299 …n) (((pin) > 42) ? (&pChipcHw->GpioSR_0_7 + (((pin) + 2) >> 3)) : (&pChipcH…
307 … (((pin) > 42) ? (&pChipcHw->GpioPull_0_15 + (((pin) + 2) >> 4)) : (&pChip…
314 …n) (((pin) > 42) ? (&pChipcHw->GpioInput_0_31 + (((pin) + 2) >> 5)) : (&pChip…
370 #define chipcHw_REG_SOFT_RESET_SPIS 0x0000000000002000ULL /* Reset SPI Slave */
371 #define chipcHw_REG_SOFT_RESET_SPIH 0x0000000000001000ULL /* Reset SPI Host */
460 …_POR_BROM 0x00000080 /* Special sticky bit for security - set in BROM to avoid…