Lines Matching +full:interconnect +full:-

15 Each of the 'cells' may be viewed as an SMP [symmetric multi-processor] subset
16 of the system--although some components necessary for a stand-alone SMP system
18 connected together with some sort of system interconnect--e.g., a crossbar or
19 point-to-point link are common types of NUMA system interconnects.  Both of
26 is handled in hardware by the processor caches and/or the system interconnect.
39 [cache misses] to be to "local" memory--memory on the same cell, if any--or
49 "closer" nodes--nodes that map to closer cells--will generally experience
61 the existing nodes--or the system memory for non-NUMA platforms--into multiple
64 application features on non-NUMA platforms, and as a sort of memory resource
69 subsystem, complete with its own free page lists, in-use page lists, usage
85 boot parameter or sysctl.  [see Documentation/kernel-parameters.txt and
97 "local" to the underlying physical resources and off the system interconnect--
100 NUMA topology of the platform--embodied in the "scheduling domains" data
101 structures [see Documentation/scheduler/sched-domains.txt]--and the scheduler
114 System administrators can restrict the CPUs and nodes' memories that a non-
120 node the "local memory node"--the node of the first zone in CPU's node's
121 zonelist--will not be the node itself.  Rather, it will be the node that the
142 If the architecture supports--does not hide--memoryless nodes, then CPUs