Lines Matching full:duty

98 a minimum pulse width of 5 clocks (at 22.5kHz => 6.25% duty cycle), and
99 a maximum pulse width of 80 clocks (at 22.5kHz => 99.88% duty cycle).
104 contains a value controlling the duty cycle for the PWM signal used when
106 indicating minimum duty cycle and 15 indicating maximum.
137 and pwm2 are used to set the manual duty cycle; each is an integer (0-255)
138 where 0 is 0% duty cycle, and 255 is 100%.  Note that the duty cycle values
141 PWM mode is disabled, the value of pwm1 and pwm2 indicates the current duty
218 A spin-up cycle occurs when a PWM output is commanded from 0% duty cycle to
219 some value > 0%.  The LM93 supports a minimum duty cycle during spin-up.  These
221 file has the same representation as other PWM duty cycle values. The
234 channel, the LM93 will ramp the PWM output up to 100% duty cycle in discrete
277 				duty cycle for the PWM signal used when
288 	pwm<n>_auto_spinup_min	minimum duty cycle during spin-up